Chris J. Myers

Curtis Madsen, Chris J. Myers, Tyler Patterson, Nicholas Roehner, Jason T. Stevens, Chris Winstead: Design and Test of Genetic Circuits Using ${\tt iBioSim}$iBioSim. IEEE Design & Test of Computers 29(3): 32-39 (2012)

Chris J. Myers: Formal Verification of Genetic Circuits. CAV 2012: 5

Curtis Madsen, Chris J. Myers, Nicholas Roehner, Chris Winstead, Zhen Zhang: Utilizing stochastic model checking to analyze genetic circuits. CIBCB 2012: 379-386

Natasa Miskov-Zivanov, James R. Faeder, Chris J. Myers, Herbert M. Sauro: Modeling and design automation of biological circuits and systems. ICCAD 2012: 291-293

Chris J. Myers, Jian Wu, Zhen Zhang, Hao Zheng, Yingying Zhang: Poster Abstract: Methods and Tools for Verification of Cyber-Physical Systems. ICCPS 2012: 232

Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers: An Improvement in Partial Order Reduction Using Behavioral Analysis. ISVLSI 2012: 100-107

Hao Zheng, Emmanuel Rodriguez, Yingying Zhang, Chris J. Myers: A Compositional Minimization Approach for Large Asynchronous Design Verification. SPIN 2012: 62-79

Scott Little, David Walter, Chris J. Myers, Robert A. Thacker, Satish Batchu, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 617-630 (2011)

Nathan A. Barker, Chris J. Myers, Hiroyuki Kuwahara: Learning Genetic Regulatory Network Connectivity from Time Series Data. IEEE/ACM Trans. Comput. Biology Bioinform. 8(1): 152-165 (2011)

Hiroyuki Kuwahara, Chris J. Myers: Erlang-delayed stochastic chemical kinetic formalism for efficient analysis of biological systems with non-elementary reaction effects. BCB 2011: 425-429

Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers: A Behavioral Analysis Approach for Efficient Partial Order Reduction. HASE 2011: 49-56

Scott Little, David Walter, Kevin R. Jones, Chris J. Myers, Alper Sen: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. Int. J. Found. Comput. Sci. 21(2): 191-210 (2010)

Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov: Temperature Control of Fimbriation Circuit Switch in Uropathogenic Escherichia coli: Quantitative Analysis via Automated Model Abstraction. PLoS Computational Biology 6(3) (2010)

Haiqiong Yao, Hao Zheng, Chris J. Myers: State space reductions for scalable verification of asynchronous designs. HLDVT 2010: 17-24

Robert A. Thacker, Kevin R. Jones, Chris J. Myers, Hao Zheng: Automatic abstraction for verification of cyber-physical systems. ICCPS 2010: 12-21

Chris Winstead, Curtis Madsen, Chris J. Myers: iSSA: An incremental stochastic simulation algorithm for genetic circuits. ISCAS 2010: 553-556

Chris J. Myers, Nathan A. Barker, Kevin R. Jones, Hiroyuki Kuwahara, Curtis Madsen, Nam-Phuong D. Nguyen: iBioSim: a tool for the analysis and design of genetic circuits. Bioinformatics 25(21): 2848-2849 (2009)

Chris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin R. Jones, Curtis Madsen, Nam-Phuong D. Nguyen: Genetic design automation. ICCAD 2009: 713-716

Robert A. Thacker, Chris J. Myers, Kevin R. Jones, Scott Little: A new verification method for embedded systems. ICCD 2009: 193-200

Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Inform. 88(4): 411-435 (2008)

Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: A Conservative Framework for Safety-Failure Checking. IEICE Transactions 91-D(3): 642-654 (2008)

Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. Journal of Computational Biology 15(7): 779-792 (2008)

David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008)

Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55

Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)

Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 592-605 (2007)

Tomohiro Yoneda, Chris J. Myers: Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1177-1195 (2007)

Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD 2007: 51-60

David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323

Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener: The Design of a Genetic Muller C-Element. ASYNC 2007: 95-104

David Walter, Scott Little, Chris J. Myers: Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81

Scott Little, David Walter, Kevin R. Jones, Chris J. Myers: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128

Scott Little, Alper Sen, Chris J. Myers: Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. MTV 2007: 109-115

Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. RECOMB 2007: 166-180

Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little: The Case for Analog Circuit Verification. Electr. Notes Theor. Comput. Sci. 153(3): 53-63 (2006)

Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)

Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov, Nathan A. Barker, Adam P. Arkin: Automated Abstraction Methodology for Genetic Regulatory Networks. : 150-175 (2006)

Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172

Tomohiro Yoneda, Chris J. Myers: Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA 2006: 229-244

Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov: Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli. BIOCOMP 2006: 125-134

Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282

Nathan A. Barker, Chris J. Myers, Hiroyuki Kuwahara: Learning Genetic Regulatory Network Connectivity from Time Series Data. IEA/AIE 2006: 962-971

Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Transactions 88-D(7): 1646-1661 (2005)

Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers: Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Transactions 88-D(11): 2555-2564 (2005)

Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers: High Level Synthesis of Timed Asynchronous Circuits. ASYNC 2005: 178-189

Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers: Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC 2004: 135-145

Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA 2004: 339-353

Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440

Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)

Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432

Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35

Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): 180-201 (2002)

Sung Tae Jung, Chris J. Myers: Direct synthesis of timed circuits from free-choice STGs. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 275-290 (2002)

Hans M. Jacobson, Chris J. Myers: Efficient algorithms for exact two-level hazard-free logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1269-1283 (2002)

Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers: Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208

Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel: Cell library for automatic synthesis of analog error control decoders. ISCAS (4) 2002: 481-484

Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220

Chris J. Myers: Asynchronous circuit design. Wiley 2001, isbn 978-0-471-41543-5, pp. I-XVII, 1-404

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)

Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel: Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147

Kip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201

Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340

Chris J. Myers, Hans M. Jacobson: Efficient Exact Two-Level Hazard-Free Logic Minimization. ASYNC 2001: 64-73

Bin Zhou, Tomohiro Yoneda, Chris J. Myers: Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium 2001: 437-442

Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193

Wendy Belluomini, Chris J. Myers: Timed state space exploration using POSETs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000)

Allen E. Sjogren, Chris J. Myers: Interfacing synchronous and asynchronous modules within a high-speed pipeline. IEEE Trans. VLSI Syst. 8(5): 573-583 (2000)

Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan: Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. ICCAD 2000: 303-310

Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 769-786 (1999)

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12

Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70

Sung Tae Jung, Chris J. Myers: Direct synthesis of timed asynchronous circuits. ICCAD 1999: 332-338

Brandon M. Bachman, Hao Zheng, Chris J. Myers: Architectural Synthesis of Timed Asynchronous Systems. ICCD 1999: 354-363

Robert A. Thacker, Wendy Belluomini, Chris J. Myers: Timed Circuit Synthesis Using Implicit Methods. VLSI Design 1999: 181-188

Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 205-219 (1998)

Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-

Wendy Belluomini, Chris J. Myers: Verification of Timed Systems Using POSETs. CAV 1998: 403-415

Allen E. Sjogren, Chris J. Myers: Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. ARVLSI 1997: 47-61

Wendy Belluomini, Chris J. Myers: Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100

Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: Automatic synthesis of gate-level timed circuits with choice. ARVLSI 1995: 42-58

Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng: Technology mapping of timed circuits. ASYNC 1995: 138-

Tomas Rokicki, Chris J. Myers: Automatic Verification of Timed Circuits. CAV 1994: 468-480

Chris J. Myers, Teresa H. Y. Meng: Synthesis of timed asynchronous circuits. IEEE Trans. VLSI Syst. 1(2): 106-119 (1993)

Chris J. Myers, Teresa H. Y. Meng: Synthesis of Timed Asynchronous Circuits. ICCD 1992: 279-284