Makoto Nagata

Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata: Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits. IEICE Transactions 96-C(4): 538-545 (2013)

Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda: A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. ISSCC 2013: 434-435

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip In-Place Measurements of V_th and Signal/Substrate Response of Differential Pair Transistors. IEICE Transactions 95-C(1): 137-145 (2012)

Makoto Nagata: Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs. IEICE Transactions 95-A(2): 430-438 (2012)

Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata: Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. IEICE Transactions 95-C(4): 586-593 (2012)

Makoto Nagata: Foreword. IEICE Transactions 95-C(6): 977 (2012)

Kumpei Yoshikawa, Yuta Sasaki, Kouji Ichikawa, Yoshiyuki Saito, Makoto Nagata: Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits. IEICE Transactions 95-A(12): 2284-2291 (2012)

Makoto Nagata, Vivek De: Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. J. Solid-State Circuits 47(4): 795-796 (2012)

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Transactions 94-C(4): 495-503 (2011)

Takushi Hashida, Yuuki Araga, Makoto Nagata: A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Transactions 94-C(6): 1016-1023 (2011)

Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Transactions 94-C(6): 1024-1031 (2011)

Takushi Hashida, Makoto Nagata: An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. J. Solid-State Circuits 46(4): 789-796 (2011)

Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne: In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6

Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh: A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92

Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61

Takushi Hashida, Yuuki Araga, Makoto Nagata: A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS 2011: 70-75

Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata: Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. IEICE Transactions 93-A(2): 440-447 (2010)

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata: An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Transactions 93-C(6): 820-826 (2010)

Takushi Hashida, Makoto Nagata: Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails. IEICE Transactions 93-C(6): 842-848 (2010)

Yuuki Araga, Takushi Hashida, Makoto Nagata: An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS 2010: 3557-3560

Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata: Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. IEICE Transactions 92-C(4): 475-482 (2009)

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata: A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC 2009: 187-190

Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata: A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. CICC 2009: 219-222

Kouji Ichikawa, Yuki Takahashi, Yukihiko Sakurai, Takahiro Tsuda, Isao Iwase, Makoto Nagata: Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation. IEICE Transactions 91-C(6): 936-944 (2008)

Takefumi Yoshikawa, Tetsuhiro Ogino, Makoto Nagata: Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications. IEICE Transactions 91-C(9): 1453-1462 (2008)

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Transactions 90-A(2): 380-387 (2007)

Masao Morimoto, Makoto Nagata, Kazuo Taki: Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Transactions 90-C(4): 675-682 (2007)

Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata: Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Transactions 90-C(4): 692-698 (2007)

Koichiro Noguchi, Takushi Hashida, Makoto Nagata: On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. IEICE Transactions 90-C(6): 1189-1196 (2007)

Kouji Ichikawa, Yuki Takahashi, Makoto Nagata: Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements. IEICE Transactions 90-C(6): 1282-1290 (2007)

Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki: A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. IEICE Transactions 90-C(6): 1299-1303 (2007)

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Transactions 90-A(12): 2651-2660 (2007)

Koichiro Noguchi, Makoto Nagata: An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. IEEE Trans. VLSI Syst. 15(10): 1101-1110 (2007)

Makoto Nagata: On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. DAC 2007: 400-403

Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki: Communication Scheme for a Highly Collision-Resistive RFID System. IEICE Transactions 89-A(2): 408-415 (2006)

Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata: Multi-Ported Register File for Reducing the Impact of PVT Variation. IEICE Transactions 89-C(3): 356-363 (2006)

Koichiro Noguchi, Makoto Nagata: An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity. IEICE Transactions 89-C(6): 761-768 (2006)

Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa: An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Transactions 89-C(11): 1535-1543 (2006)

Mitsuya Fukazawa, Makoto Nagata: Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. IEICE Transactions 89-C(11): 1559-1566 (2006)

Yohei Fukumizu, Makoto Nagata, Kazuo Taki: Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. IEICE Transactions 89-C(11): 1581-1590 (2006)

Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki: A built-in power supply noise probe for digital LSIs. ASP-DAC 2006: 106-107

Daisuke Kosaka, Makoto Nagata: Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. ASP-DAC 2006: 677-682

Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa: Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. IEICE Transactions 88-C(4): 589-596 (2005)

Masao Morimoto, Makoto Nagata, Kazuo Taki: High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Transactions 88-C(10): 2001-2008 (2005)

Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki: Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Transactions 88-A(12): 3324-3331 (2005)

Koichiro Noguchi, Makoto Nagata: On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. DATE 2005: 146-151

Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200

Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76

Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487

Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122

Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000)

Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20

Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24

Makoto Nagata, Atsushi Iwata: Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC 2000: 623-630

Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88

Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585

Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589