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 | 2012 | |
|---|---|---|
| j3 |      | Allon Adir, Amir Nahir, Avi Ziv: Concurrent Generation of Concurrent Programs for Post-Silicon Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1297-1302 (2012) |
| c18 | | Amir Nahir, Avi Ziv, Subrat Panda: Optimizing test-generation to the execution platform. ASP-DAC 2012: 304-309 |
| c17 | | Flavio M. de Paula, Alan J. Hu, Amir Nahir: nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces. CAV 2012: 513-531 |
| c16 | | Amir Nahir, Ariel Orda, Danny Raz: Distributed oblivious load balancing using prioritized job replication. CNSM 2012: 55-63 |
| c15 | | Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco: Approximating checkers for simulation acceleration. DATE 2012: 153-158 |
| c14 | | Amir Nahir, Ariel Orda, Danny Raz: Workload factoring with the cloud: A game-theoretic perspective. INFOCOM 2012: 2566-2570 |
| 2011 | ||
| c13 | | Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigail Orni, Alan J. Hu: TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead. DAC 2011: 411-416 |
| c12 | | Allon Adir, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann: Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor. DAC 2011: 569-574 |
| c11 | | Allon Adir, Maxim Golubev, Shimon Landa, Amir Nahir, Gil Shurek, Vitali Sokhin, Avi Ziv: Threadmill: a post-silicon exerciser for multi-threaded processors. DAC 2011: 860-865 |
| c10 | | Allon Adir, Shady Copty, Shimon Landa, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann: A unified methodology for pre-silicon verification and post-silicon validation. DATE 2011: 1590-1595 |
| 2010 | ||
| j2 | | David Breitgand, Rami Cohen, Amir Nahir, Danny Raz: On cost-aware monitoring for self-adaptive load sharing. IEEE Journal on Selected Areas in Communications 28(1): 70-83 (2010) |
| c9 | | Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor: Bridging pre-silicon verification and post-silicon validation. DAC 2010: 94-95 |
| c8 | | Allon Adir, Amir Nahir, Avi Ziv, Charles Meissner, John Schumann: Reaching Coverage Closure in Post-silicon Validation. Haifa Verification Conference 2010: 60-75 |
| 2009 | ||
| j1 | | Cindy Eisner, Amir Nahir, Karen Yorav: Functional verification of power gated designs by compositional reasoning. Formal Methods in System Design 35(1): 40-55 (2009) |
| c7 | | Amir Nahir, Ariel Orda, A. Freund: Topology Design and Control: A Game-Theoretic Perspective. INFOCOM 2009: 1620-1628 |
| 2008 | ||
| c6 | | Cindy Eisner, Amir Nahir, Karen Yorav: Functional Verification of Power Gated Designs by Compositional Reasoning. CAV 2008: 433-445 |
| 2007 | ||
| c5 | | David Breitgand, Rami Cohen, Amir Nahir, Danny Raz: On Fully Distributed Adaptive Load Balancing. DSOM 2007: 74-85 |
| c4 | | David Breitgand, Rami Cohen, Amir Nahir, Danny Raz: Using the Right Amount of Monitoring in Adaptive Load Sharing. ICAC 2007: 7 |
| c3 | | David Breitgand, Rami Cohen, Amir Nahir, Danny Raz: Cost Aware Adaptive Load Sharing. IWSOS 2007: 208-224 |
| 2006 | ||
| c2 | | Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen: Scheduling-based test-case generation for verification of multimedia SoCs. DAC 2006: 348-351 |
| c1 | | Amir Nahir, Yossi Shiloach, Avi Ziv: Using Linear Programming Techniques for Scheduling-Based Random Test-Case Generation. Haifa Verification Conference 2006: 16-33 |
Colors in the list of coauthors
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