O. Sam Nakagawa

Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002)

Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie: Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED 2001: 185-190

Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa: Instruction Prediction for Step Power Reduction. ISQED 2001: 211-216

Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He: Clocktree RLC Extraction with Efficient Inductance Modeling. DATE 2000: 522-526

Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie: Full Chip Thermal Simulation. ISQED 2000: 145-150

Shen Lin, Norman Chang, O. Sam Nakagawa: Quick On-Chip Self- and Mutual-Inductance Screen. ISQED 2000: 513-

Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He: Ramp Up/Down Functional Unit to Reduce Step Power. PACS 2000: 13-24

Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh: Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. ICCD 1997: 720-725

Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, J. Moll: A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. ICCD 1996: 320-325