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Kazuhiro Nakamura
2010 – today
- 2012
[j4]Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi: A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition. IEICE Transactions 95-C(4): 456-467 (2012)- 2010
- [j3]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi: A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing. IEICE Transactions 93-D(2): 300-305 (2010)
2000 – 2009
- 2008
- [c9]Yoshihiko Nankaku, Kazuhiro Nakamura, Heiga Zen, Keiichi Tokuda: Acoustic modeling with contextual additive structure for HMM-based speech recognition. ICASSP 2008: 4469-4472
- [c8]Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi: Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS 2008: 1688-1691
- 2007
- [c7]Shigeo Shioda, Kazuhiro Nakamura: Scale-Free Property of Directed Networks with Two Intrinsic Node Weights. GLOBECOM 2007: 532-537
- 2004
- [j2]Satoshi Yamane, Kazuhiro Nakamura: Development and evaluation of symbolic model checker based on approximation for real-time systems. Systems and Computers in Japan 35(10): 83-101 (2004)
- 2001
- [c6]Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC 2001: 31-32
- [c5]Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: Speech recognition chip for monosyllables. ASP-DAC 2001: 396-399
- 2000
- [c4]Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe: Multi-clock path analysis using propositional satisfiability. ASP-DAC 2000: 81-86
1990 – 1999
- 1998
- [c3]Kazuhiro Nakamura, Satoshi Yamane: Formal Verification of Real-Time Software by Symbolic Model-Checker. ACSD 1998: 99-108
- [c2]Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe: Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395
- 1997
- [j1]Kazuhiro Nakamura, Yoshiyuki Aono, Yoshiaki Tadokoro: A walking navigation system for the blind. Systems and Computers in Japan 28(13): 36-45 (1997)
- [c1]Satoshi Yamane, Kazuhiro Nakamura: Symbolic Model-Checking Method Based on Approximations and Binary Decision Diagrams for Real-Time Systems. TACS 1997: 562-582
Coauthor Index
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last updated on 2012-12-02 21:14 CET by the dblp team