| 2013 | ||
|---|---|---|
| j6 | Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. IEICE Transactions 96-D(1): 1-8 (2013) | |
| 2012 | ||
| j5 | Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Quantum Walks on the Line with Phase Parameters. IEICE Transactions 95-D(3): 722-730 (2012) | |
| j4 | Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima: RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. IEICE Transactions 95-A(12): 2319-2329 (2012) | |
| c16 | Kazutaka Kamimura, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima: A Speed-up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions. ICNC 2012: 49-57 | |
| c15 | Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. TAMC 2012: 400-411 | |
| i2 | Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. CoRR abs/1202.6444 (2012) | |
| i1 | Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. Electronic Colloquium on Computational Complexity (ECCC) 19: 4 (2012) | |
| 2011 | ||
| j3 | Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima: An Instruction Mapping Scheme for FU Array Accelerator. IEICE Transactions 94-D(2): 286-297 (2011) | |
| j2 | Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Information & Computation 11(1&2): 142-166 (2011) | |
| c14 | Ryosuke Oda, Tatsuhiro Yamada, Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima: Input Entry Integration for an Auto-Memoization Processor. ICNC 2011: 179-185 | |
| c13 | Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima: LAPP: A Low Power Array Accelerator with Binary Compatibility. IPDPS Workshops 2011: 854-862 | |
| 2010 | ||
| c12 | Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima: A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations. ICNC 2010: 63-70 | |
| c11 | Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi: A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC 2010: 237-238 | |
| 2009 | ||
| j1 | Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. Quantum Information & Computation 9(5): 423-443 (2009) | |
| c10 | Yushi Kamiya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima: A Speculative Technique for Auto-Memoization Processor with Multithreading. PDCAT 2009: 160-166 | |
| 2008 | ||
| c9 | Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: A Functional Unit with Small Variety of Highly Reliable Cells. PRDC 2008: 353-354 | |
| 2007 | ||
| c8 | Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC 2007: 343-349 | |
| c7 | Tomoaki Tsumura, Ikuma Suzuki, Yasuki Ikeuchi, Hiroshi Matsuo, Hiroshi Nakashima, Yasuhiko Nakashima: Design and evaluation of an auto-memoization processor. Parallel and Distributed Computing and Networks 2007: 230-235 | |
| 2005 | ||
| c6 | Jun Yao, Hajime Shimada, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita: Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption. ISHPC 2005: 494-507 | |
| 2004 | ||
| c5 | Kenji Satou, Yasuhiko Nakashima, Shin'ichi Tsuji, Xavier Défago, Akihiko Konagaya: An Integrated System for Distributed Bioinformatics Environment on Grids. LSGRID 2004: 8-19 | |
| c4 | Alam Mujahid, Koh Kakusho, Michihiko Minoh, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita: Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP. Parallel and Distributed Computing and Networks 2004: 386-391 | |
| c3 | Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita: Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. PDPTA 2004: 373-382 | |
| 2001 | ||
| c2 | Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori: A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO 2001: 225-236 | |
| 1995 | ||
| c1 | Yasuhiko Nakashima, Toshiaki Kitamura, Hideo Tamura, Masaaki Takiuchi, Ken'ichi Miura: Scalar Processor of the VPP500 Parallel Supercomputer. International Conference on Supercomputing 1995: 348-356 | |
Colors in the list of coauthors
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