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Yohei Nakata
2010 – today
- 2013
[j3]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Transactions 96-C(4): 528-537 (2013)- [c9]Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi: Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. ISQED 2013: 216-222
- 2012
- [j2]Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Transactions 95-C(4): 523-533 (2012)
- [c8]Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384
- [c7]Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519
- 2011
- [j1]Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Transactions 94-A(12): 2693-2700 (2011)
- [c6]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4
- [c5]Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804
- [c4]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527
- [c3]Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto: Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325
- 2010
- [c2]Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4
- [c1]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224
Coauthor Index
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last updated on 2013-06-11 21:34 CEST by the dblp team