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Mitaro Namiki
2010 – today
- 2013
[j4]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki: Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Transactions 96-C(4): 404-412 (2013)- [c29]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa: A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI. PDP 2013: 249-253
- 2012
- [c28]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546
- [c27]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296
- [c26]Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Mikiko Sato, Mitaro Namiki, Yutaka Ishikawa: Delegation-Based MPI Communications for a Hybrid Parallel Computer with Many-Core Architecture. EuroMPI 2012: 47-56
- [c25]Atsushi Hori, Toyohisa Kameyama, Yuichi Tsujita, Mitaro Namiki, Yutaka Ishikawa: An Efficient Kernel-Level Blocking MPI Implementation. EuroMPI 2012: 153-162
- [c24]Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki: An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422
- 2011
- [j3]Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano: A Leakage Efficient Data TLB Design for Embedded Processors. IEICE Transactions 94-D(1): 51-59 (2011)
- [j2]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano: A Leakage Efficient Instruction TLB Design for Embedded Processors. IEICE Transactions 94-D(8): 1565-1574 (2011)
- [j1]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011)
- [c23]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo: Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88
- [c22]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8
- [c21]Mikiko Sato, Yuji Sato, Mitaro Namiki: Acceleration experiment of genetic computations for sudoku solution on multi-core processors. GECCO (Companion) 2011: 823-824
- [c20]Hiroki Manabe, Susumu Kanemune, Mitaro Namiki, Yoshiaki Nakano: CS Unplugged Assisted by Digital Materials for Handicapped People at Schools. ISSEP 2011: 82-93
- 2010
- [c19]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo: Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370
- [c18]Mikiko Sato, Yuji Sato, Mitaro Namiki: Proposal of a multi-core processor from the viewpoint of evolutionary computation. IEEE Congress on Evolutionary Computation 2010: 1-8
- [c17]Mikiko Sato, Yuji Sato, Mitaro Namiki: Proposal of a multi-core processor architecture for effective evolutionary computation. GECCO 2010: 1321-1322
- [c16]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki: Reducing instruction TLB's leakage power consumption for embedded processors. Green Computing Conference 2010: 477-484
- [c15]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37
2000 – 2009
- 2009
- [c14]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara: Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517
- [c13]Tomohiro Nishida, Susumu Kanemune, Yukio Idosaka, Mitaro Namiki, Tim Bell, Yasushi Kuno: A CS unplugged design pattern. SIGCSE 2009: 231-235
- [c12]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura: Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386
- 2008
- [c11]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617
- 2007
- [c10]Jun Kanai, Mitaro Namiki, Kuniyasu Suzaki, Toshiki Yagi: Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX". PDPTA 2007: 207-213
- 2006
- [c9]Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki: Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA 2006: 902-908
- [c8]Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo: A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915
- [c7]Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo: Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924
- 2005
- [c6]Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453
- [c5]Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460
- 2004
- [c4]Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323
- 2003
- [c3]Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615
- [c2]Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675
- [c1]Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781
Coauthor Index
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last updated on 2013-04-19 20:46 CEST by the dblp team