| 2007 | ||
|---|---|---|
| j4 | Ricardo Carretero-González, Panayotis G. Kevrekidis, D. J. Frantzeskakis, Boris A. Malomed, S. Nandi, A. R. Bishop: Soliton trains and vortex streets as a form of Cerenkov radiation in trapped Bose-Einstein condensates. Mathematics and Computers in Simulation 74(4-5): 361-369 (2007) | |
| 2005 | ||
| c10 | ||
| c9 | R. Mukherjee, S. Nandi, S. Banerjee: Reduction in spectral peaks of DC-DC converters using chaos-modulated clock. ISCAS (4) 2005: 3367-3370 | |
| 1999 | ||
| c8 | N. Sudha, S. Nandi, K. Sridharan: A Parallel Algorithm to Construct Voronoi Diagram and Its VLSI Architecture. ICRA 1999: 1683-1688 | |
| c7 | S. Nandi, Ch. Rambabu, Parimal Pal Chaudhuri: A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder. ISPAN 1999: 158-167 | |
| 1997 | ||
| j3 | S. Nandi, Parimal Pal Chaudhuri: Reply to Comments on "Theory and Application of Cellular Automata in Cryptography". IEEE Trans. Computers 46(5): 639 (1997) | |
| c6 | ||
| 1996 | ||
| j2 | S. Nandi, Parimal Pal Chaudhuri: Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata. IEEE Trans. Computers 45(1): 1-12 (1996) | |
| c5 | S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri: Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. VLSI Design 1996: 61-64 | |
| c4 | S. Mitra, S. Das, Parimal Pal Chaudhuri, S. Nandi: Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. VLSI Design 1996: 316-317 | |
| 1995 | ||
| c3 | S. Nandi, Parimal Pal Chaudhuri: Theory and applications of cellular automata for synthesis of easily testable combinational logic. Asian Test Symposium 1995: 146-152 | |
| 1994 | ||
| j1 | S. Nandi, B. K. Kar, Parimal Pal Chaudhuri: Theory and Applications of Cellular Automata in Cryptography. IEEE Trans. Computers 43(12): 1346-1357 (1994) | |
| c2 | S. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri: A CAD Tool for Design of On-Chip Store & Generate Scheme. VLSI Design 1994: 169-174 | |
| 1993 | ||
| c1 | S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy: Delay Fault Test Generation with Cellular Automata. VLSI Design 1993: 281-286 | |
Colors in the list of coauthors
Last update Wed May 22 19:55:04 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page