Edwin Naroska

Todor Dimitrov, Josef Pauli, Edwin Naroska: Unsupervised Recognition of ADLs. SETN 2010: 71-80

Yu-Ting Pai, Chia-Han Lee, Shanq-Jang Ruan, Edwin Naroska: An improved comparison circuit for low power pre-computation-based content-addressable memory designs. ICECS 2009: 663-666

Ayseguel Dogangün, Tobias Haverkamp, Marco Munstermann, Gudrun Stockmanns, Edwin Naroska: "inBath" - assistive Badumgebung. Mensch & Computer 2009: 423-426

Todor Dimitrov, Josef Pauli, Edwin Naroska, Christian Ressel: Structured Learning of Component Dependencies in AmI Systems. IAT 2008: 118-124

Todor Dimitrov, Josef Pauli, Edwin Naroska: A probabilistic reasoning framework for smart homes. MPAC 2007: 1-6

Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn: Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. IEEE Trans. VLSI Syst. 14(4): 421-425 (2006)

Jörg Platte, Edwin Naroska, Kai Grundmann: A Cache Design for a Security Architecture for Microprocessors (SAM). ARCS 2006: 435-449

Jörg Platte, Raúl Durán Díaz, Edwin Naroska: A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors. Communications and Multimedia Security 2006: 120-129

Jörg Platte, Raúl Durán Díaz, Edwin Naroska: An Operating System Design for the Security Architecture for Microprocessors. ICICS 2006: 174-189

Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen: Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ISPD 2006: 114-119

Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai: Bipartitioning and encoding in low-power pipelined circuits. ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005)

Jörg Platte, Edwin Naroska: A combined hardware and software architecture for secure computing. Conf. Computing Frontiers 2005: 280-288

Uwe Schwiegelshohn, Edwin Naroska: Verlustleistungsarme Fehlerschutzprotokolle basierend auf punktierten Low Density Parity Check Codes (LDPC). GI Jahrestagung (1) 2005: 461

Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. IPDPS 2005

Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn: An efficient algorithm for simultaneous wire permutation, inversion, and spacing. ISCAS (1) 2005: 109-112

Peter Schramm, Edwin Naroska, Peter Resch, Jörg Platte, Holger Linde, Guido Stromberg, Thomas F. Sturm: A Service Gateway for Networked Sensor Systems. IEEE Pervasive Computing 3(1): 66-74 (2004)

Uwe Dammer, Edwin Naroska, Stefan Schmermbeck, Uwe Schwiegelshohn: A data puncturing IR-scheme for type-II hybrid ARQ protocols using LDPC codes. GLOBECOM 2004: 3012-3016

Edwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn: A novel approach for digital waveform compression. ASP-DAC 2003: 712-715

Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu: On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. ISCAS (5) 2003: 277-280

Edwin Naroska, Uwe Schwiegelshohn: On an on-line scheduling problem for parallel jobs. Inf. Process. Lett. 81(6): 297-304 (2002)

Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn: ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. VLSI Syst. 10(6): 942-949 (2002)

Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai: Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11

Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai: Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. ICCD 2002: 327-

Edwin Naroska, Feipei Lai, Rung-Ji Shang, Uwe Schwiegelshohn: Efficient parallel timing simulation of synchronous models on networks of workstations. Journal of Systems Architecture 47(6): 517-528 (2001)

Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn: Hybrid Parallel Circuit Simulation Approaches. IEEE PACT 2000: 261-270

Edwin Naroska, Uwe Schwiegelshohn: Conservative Parallel Simulation of a Large Number of Processes. Simulation 72(3): 150-162 (1999)

Edwin Naroska: Parallel VHDL Simulation. DATE 1998: 159-163

Edwin Naroska, Uwe Schwiegelshohn: A New Scheduling Method for Parallel Discrete-Event Simulation. Euro-Par, Vol. II 1996: 582-593