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Sani R. Nassif
2010 – today
- 2013
[j21]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta: Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 202-215 (2013)- [c100]Jörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn: Reliable on-chip systems in the nano-era: lessons learnt and future trends. DAC 2013: 99
- [c99]Thomas H. Osiecki, Min-yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze: Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. ICCS 2013: 2241-2250
- [c98]Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif: SRAM bit-line electromigration mechanism and its prevention scheme. ISQED 2013: 286-293
- [c97]Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee: Wire delay variability in nanoscale technology and its impact on physical design. ISQED 2013: 591-596
- 2012
- [j20]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan: An accurate sparse-matrix based framework for statistical static timing analysis. Integration 45(4): 365-375 (2012)
- [c96]Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman: Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC 2012: 7-16
- [c95]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif: Yield estimation via multi-cones. DAC 2012: 1107-1112
- [c94]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif: 2012 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2012: 643-646
- [c93]
- [c92]Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham: An oscillation-based test structure for timing information extraction. VTS 2012: 74-79
- 2011
- [j19]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif: Hierarchical Multialgorithm Parallel Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 45-58 (2011)
- [j18]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Simultaneous Layout Migration and Decomposition for Double Patterning Technology. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 284-294 (2011)
- [j17]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka: The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. IEEE Trans. on Circuits and Systems 58-I(9): 2010-2016 (2011)
- [j16]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011 (2011)
- [c91]Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham: Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium 2011: 232-237
- [c90]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif: Electrically-driven retargeting for nanoscale layouts. CICC 2011: 1-4
- [c89]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta: A framework for double patterning-enabled design. ICCAD 2011: 14-20
- [c88]Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif: Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360
- [c87]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif: 2011 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2011: 478-481
- [c86]Mehrdad Majzoobi, Golsa Ghiaasi, Farinaz Koushanfar, Sani R. Nassif: Ultra-low power current-based PUF. ISCAS 2011: 2071-2074
- [c85]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky: Coupling timing objectives with optical proximity correction for improved timing yield. ISQED 2011: 97-102
- [c84]Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham: Efficient and product-representative timing model validation. VTS 2011: 90-95
- 2010
- [j15]
- [j14]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao: Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. VLSI Syst. 18(4): 666-670 (2010)
- [c83]
- [c82]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka: A 32nm 0.5V-supply dual-read 6T SRAM. CICC 2010: 1-4
- [c81]
- [c80]Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky: A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278
- [c79]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Template-mask design methodology for double patterning technology. ICCAD 2010: 107-111
- [c78]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED 2010: 337-342
- [c77]
2000 – 2009
- 2009
- [c76]Sherief Reda, Sani R. Nassif: Analyzing the impact of process variations on parametric measurements: Novel models and applications. DATE 2009: 375-380
- [c75]Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif: An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD 2009: 497-504
- [c74]Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Simultaneous layout migration and decomposition for double patterning technology. ICCAD 2009: 595-600
- [c73]Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das: Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD 2009: 631-636
- [c72]Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka: Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194
- [c71]Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi: The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612
- 2008
- [b1]Michael Orshansky, Sani R. Nassif, Duane S. Boning: Design for Manufacturability and Statistical Design - A Constructive Approach. Series on integrated circuits and systems, Springer 2008, ISBN 978-0-387-30928-6, pp. I-XIV, 1-310
- [j13]Kanak Agarwal, Sani R. Nassif: The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. IEEE Trans. VLSI Syst. 16(1): 86-97 (2008)
- [c70]
- [c69]
- [c68]Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham: Analytical model for the impact of multiple input switching noise on timing. ASP-DAC 2008: 514-517
- [c67]
- [c66]Diana Marculescu, Sani R. Nassif: Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. DATE 2008
- [c65]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif: MAPS: multi-algorithm parallel circuit simulation. ICCAD 2008: 73-78
- [c64]Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif: SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92
- [c63]Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif: Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707
- [c62]Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic: A Design Model for Random Process Variability. ISQED 2008: 734-737
- [c61]Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif: A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809
- [c60]
- [c59]Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif: Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. VLSI Design 2008: 14-15
- [e1]Sani R. Nassif, Jaijeet S. Roychowdhury (Eds.): 2008 International Conference on Computer-Aided Design (ICCAD'08), November 10-13, 2008, San Jose, CA, USA. IEEE 2008, ISBN 978-1-4244-2820-5
- 2007
- [c58]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
- [c57]Kanak Agarwal, Sani R. Nassif: Characterizing Process Variation in Nanometer CMOS. DAC 2007: 396-399
- [c56]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao: Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. DAC 2007: 823-828
- [c55]Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66
- [c54]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif: Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40
- [i1]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. CoRR abs/0710.4654 (2007)
- 2006
- [j12]T. M. Mak, Sani R. Nassif: Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Design & Test of Computers 23(6): 436-437 (2006)
- [j11]Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer: High-performance CMOS variability in the 65-nm regime and beyond. IBM Journal of Research and Development 50(4-5): 433-450 (2006)
- [c53]
- [c52]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72
- [c51]Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412
- [c50]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
- [c49]Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky: Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322
- [c48]Emrah Acar, Kanak Agarwal, Sani R. Nassif: Characterization of total chip leakage using inverse (reciprocal) gamma distribution. ISCAS 2006
- [c47]Sani R. Nassif, Kanak Agarwal, Emrah Acar: Methods for estimating decoupling capacitance of nonswitching circuit blocks. ISCAS 2006
- [c46]
- [c45]Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif: System-Level SRAM Yield Enhancement. ISQED 2006: 179-184
- [c44]Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif: SRAM Local Bit Line Access Failure Analyses. ISQED 2006: 204-209
- [c43]Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif: Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649
- 2005
- [j10]Emrah Acar, Anirudh Devgan, Sani R. Nassif: Leakage and Leakage Sensitivity Computation for Combinational Circuits. J. Low Power Electronics 1(2): 172-181 (2005)
- [j9]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 676-682 (2005)
- [j8]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Power grid analysis using random walks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1204-1224 (2005)
- [c42]Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse: The Titanic: what went wrong! DAC 2005: 349-350
- [c41]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE 2005: 958-963
- [c40]Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif: Benefits and Costs of Power-Gating Technique. ICCD 2005: 559-566
- [c39]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607
- [c38]Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
- [c37]
- [c36]Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham: Testing and debugging delay faults in dynamic circuits. ITC 2005: 10
- [c35]Anirudh Devgan, Sani R. Nassif: Power Variability and Its Impact on Design. VLSI Design 2005: 679-682
- 2004
- [j7]Juan Antonio Carballo, Sani R. Nassif: Impact of Design-Manufacturing Interface on SoC Design Methodologies. IEEE Design & Test of Computers 21(3): 183-191 (2004)
- [j6]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)
- [c34]Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
- [c33]Sani R. Nassif, Duane S. Boning, Nagib Hakim: The care and feeding of your statistical static timer. ICCAD 2004: 138-139
- [c32]Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar: A chip-level electrostatic discharge simulation strategy. ICCAD 2004: 315-318
- [c31]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193
- [c30]
- [c29]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. ISPD 2004: 132-137
- 2003
- [j5]Sani R. Nassif, Soha Hassoun: Guest Editors' Introduction: On-Chip Power Distribution Networks. IEEE Design & Test of Computers 20(3): 5-6 (2003)
- [j4]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif: Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 428-436 (2003)
- [c28]Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif: Predicting short circuit power from timing models. ASP-DAC 2003: 277-282
- [c27]Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Random walks in a supply network. DAC 2003: 93-98
- [c26]Haihua Su, Emrah Acar, Sani R. Nassif: Power grid reduction based on algebraic multigrid principles. DAC 2003: 109-112
- [c25]Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif: Full chip leakage estimation considering power supply and temperature variations. ISLPED 2003: 78-83
- [c24]Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns: Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99
- [c23]Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif: Optimal shielding/spacing metrics for low power design. ISVLSI 2003: 167-172
- 2002
- [j3]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm: A multigrid-like technique for power grid analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1148-1160 (2002)
- [c22]Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69
- [c21]Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi: A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE 2002: 568-575
- [c20]Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long: Static timing analysis based circuit-limited-yield estimation. ISCAS (5) 2002: 81-84
- [c19]Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif: An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD 2002: 68-73
- [c18]Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi: Time-Domain Simulation of Variational Interconnect Models. ISQED 2002: 419-424
- [c17]Juan Antonio Carballo, Sani R. Nassif: Impact of Technology in Power-Grid-Induced Noise. PATMOS 2002: 45-54
- [c16]
- [c15]Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu: Test structures for delay variability. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 109
- 2001
- [c14]Sani R. Nassif: Modeling and forecasting of manufacturing variations (embedded tutorial). ASP-DAC 2001: 145-150
- [c13]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori: Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268
- [c12]Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm: Multigrid-Like Technique for Power Grid Analysis. ICCAD 2001: 480-487
- [c11]Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu: Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED 2001: 431-436
- [c10]Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long: Timing Yield Estimation from Static Timing Analysis. ISQED 2001: 437-442
- 2000
- [c9]
- [c8]Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas: Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171
- [c7]Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha Chandrakasan, Rakesh Vallishayee, Sani R. Nassif: A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. DAC 2000: 172-175
- [c6]N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang: When bad things happen to good chips (panel session). DAC 2000: 736-737
- [c5]
- [c4]
1990 – 1999
- 1999
- [c3]
- 1997
- [c2]David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif: Physical design challenges for performance. ISPD 1997: 225-226
1980 – 1989
- 1986
- [j2]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director: A Methodology for Worst-Case Analysis of Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 104-113 (1986)
- [c1]Luís M. Vidigal, Sani R. Nassif, Stephen W. Director: CINNAMON: coupled integration and nodal analysis of MOS networks. DAC 1986: 179-185
- 1984
- [j1]Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director: FABRICS II: A Statistically Based IC Fabrication Process Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 3(1): 40-46 (1984)
Coauthor Index
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last updated on 2013-06-11 21:50 CEST by the dblp team