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Zainalabedin Navabi
2010 – today
- 2012
[c94]Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi: A Probabilistic and Constraint Based Approach for Low Power Test Generation. Asian Test Symposium 2012: 113-118- [c93]M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi: Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS 2012: 42-45
- [c92]Parisa Kabiri, Zainalabedin Navabi: Effective RT-level software-based self-testing of embedded processor cores. DDECS 2012: 209-212
- [c91]Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi: Soft Error Analysis on Communication Channels in On-Chip Communication Networks. DSD 2012: 852-857
- [c90]Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi: BS 1149.1 extensions for an online interconnect fault detection and recovery. ITC 2012: 1-9
- [c89]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita: Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. MEMOCODE 2012: 65-74
- 2011
- [c88]Nastaran Nemati, Zainalabedin Navabi: Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. Asian Test Symposium 2011: 72-77
- [c87]Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi: Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. Asian Test Symposium 2011: 114-119
- [c86]B. Khodabandeloo, Seyyed Alireza Hoseini, S. Taheri, M. H. Haghbayan, M. R. Babaei, Zainalabedin Navabi: Online Test Macro Scheduling and Assignment in MPSoC Design. Asian Test Symposium 2011: 148-153
- [c85]Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi: Configurable architecture for memory BIST. EWDTS 2011: 1-5
- 2010
- [j17]Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi: EDXY - A low cost congestion-aware routing algorithm for network-on-chips. Journal of Systems Architecture - Embedded Systems Design 56(7): 256-264 (2010)
- [j16]Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi: Real-time embedded emotional controller. Neural Computing and Applications 19(1): 13-19 (2010)
- [c84]M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi: Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. Asian Test Symposium 2010: 53-56
- [c83]S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi: A reconfigurable online BIST for combinational hardware using digital neural networks. European Test Symposium 2010: 139-144
- [c82]Fatemeh Javaheri, Zainalabedin Navabi: ESL design methodology for architecture exploration. EWDTS 2010: 395-401
- [c81]Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi: A TLM2.0 assertion library with centralized monitoring approach. EWDTS 2010: 402-406
- [c80]Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi: Virtual tester development using HDL/PLI. EWDTS 2010: 412-415
- [c79]Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi: Merit based directed random test generation (MDRTG) scheme for combinational circuits. EWDTS 2010: 416-419
- [c78]Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi: Near optimal machine learning based random test generation. EWDTS 2010: 420-424
- [c77]Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi: Facilitating testability of TLM FIFO: SystemC implementations. EWDTS 2010: 428-431
- [c76]Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi: Code optimization for enhancing SystemC simulation time. EWDTS 2010: 431-434
- [c75]Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi: Generating test patterns for sequential circuits using random patterns by PLI functions. EWDTS 2010: 456-461
- [c74]M. H. Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi: Low cost error tolerant motion estimation for H.264/AVC standard. EWDTS 2010: 461-465
- [c73]M. H. Haghbayan, Zainalabedin Navabi: Architecture design and technical methodology for bus testing. EWDTS 2010: 504-509
- [c72]Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi: Assertion based verification in TLM. EWDTS 2010: 509-513
- [c71]Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi: A mixed HDL/PLI test package. EWDTS 2010: 518-523
- [c70]Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi: A partitioning approach to improve reconfigurable neuron-inspired online BIST. IOLTS 2010: 173-178
- [c69]Sara Karamati, Zainalabedin Navabi: Using context based methods for test data compression. ITC 2010: 809
2000 – 2009
- 2009
- [j15]Mohammad Reza Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi: Emotion on FPGA: Model driven approach. Expert Syst. Appl. 36(4): 7369-7378 (2009)
- [j14]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Sign Bit Reduction Encoding For Low Power Applications. Signal Processing Systems 57(3): 321-329 (2009)
- [c68]Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi: Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. DFT 2009: 268-276
- 2008
- [j13]Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi: Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults. J. UCS 14(22): 3716-3736 (2008)
- [j12]Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi: A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008)
- [c67]Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi: BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. DATE 2008: 1408-1413
- [c66]Nadereh Hatami, Zainalabedin Navabi: An advanced method for synthesizing TLM2-based interfaces. EWDTS 2008: 104-108
- [c65]Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi: An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. EWDTS 2008: 178-181
- [c64]Negin Mahani, Parnian Mokri, Zainalabedin Navabi: System level hardware design and simulation with SystemAda. EWDTS 2008: 190-193
- [c63]Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi: Automating Hardware/Software partitioning using dependency Graph. EWDTS 2008: 196-199
- [c62]Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi: Reliable NoC architecture utilizing a robust rerouting algorithm. EWDTS 2008: 200-203
- [c61]Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi: Utilizing HDL simulation engines for accelerating design and test processes. EWDTS 2008: 371-375
- [c60]Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto: Functional testing approaches for "BIFST-able" tlm_fifo. HLDVT 2008: 85-92
- [c59]Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi: A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. IOLTS 2008: 173-174
- [c58]Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi: Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS 2008: 207-212
- [c57]Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi: NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. ITC 2008: 1
- [c56]Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi: "Plug & Test" at System Level via Testable TLM Primitives. ITC 2008: 1-10
- [c55]Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi: An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. VLSI Design 2008: 409-414
- [c54]Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi: Enhanced TED: A New Data Structure for RTL Verification. VLSI Design 2008: 481-486
- [c53]Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi: Stall Power Reduction in Pipelined Architecture Processors. VLSI Design 2008: 541-546
- 2007
- [j11]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi: Low overhead DFT using CDFG by modifying controller. IET Computers & Digital Techniques 1(4): 322-333 (2007)
- [j10]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi: Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2) (2007)
- [c52]Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi: Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366
- [c51]Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250
- [c50]Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi: Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT 2007: 21-30
- [c49]Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538
- [c48]Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. FDL 2007: 50-55
- [c47]Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi: A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL 2007: 171-176
- [c46]Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi: RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI 2007: 172-175
- [c45]Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi: An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56
- [c44]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206
- [c43]Ali Shahabi, Nima Honarmand, Zainalabedin Navabi: Programmable Routing Tables for Degradable Torus-Based Networks on Chips. ISCAS 2007: 1065-1068
- [c42]Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi: A New Approach for Design and Verification of Transaction Level Models. ISCAS 2007: 3760-3763
- [c41]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi: A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248
- [c40]Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi: High Level Synthesis of Degradable ASICs Using Virtual Binding. VTS 2007: 311-317
- [i1]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures. CoRR abs/0710.4653 (2007)
- 2006
- [j9]Ehsan Atoofian, Zainalabedin Navabi: A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. 21(1): 141-146 (2006)
- [j8]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electronics 2(3): 477-487 (2006)
- [c39]Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi: NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP 2006: 33-38
- [c38]Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi: A concurrent testing method for NoC switches. DATE 2006: 1171-1176
- [c37]Hadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie: DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS 2006
- [c36]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Low-power and low-latency cluster topology for local traffic NoCs. ISCAS 2006
- [c35]Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi: An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI 2006: 420-421
- [c34]Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi: A New Protocol Stack Model for Network on Chip. ISVLSI 2006: 440-441
- [c33]Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi: Ant colony based routing architecture for minimizing hot spots in NOCs. SBCCI 2006: 56-61
- [c32]Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi: ByZFAD: a low switching activity architecture for shift-and-add multipliers. SBCCI 2006: 179-183
- 2005
- [b1]Zainalabedin Navabi: Digital design and implementation with field programmable devices. Kluwer 2005, ISBN 978-1-4020-8011-1, pp. I-XVI, 1-293
- [j7]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005)
- [c31]Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi: TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572
- [c30]Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi: ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241
- [c29]Shahrzad Mirkhani, Zainalabedin Navabi: Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium 2005: 278-283
- [c28]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi: Sign bit reduction encoding for low power applications. DAC 2005: 214-217
- [c27]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851
- [c26]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT 2005: 389-397
- [c25]Mostafa Naderi, Zainalabedin Navabi: Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. FDL 2005: 479-485
- [c24]Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi: Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427
- [c23]Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha: A low-power scan-path architecture. ISCAS (5) 2005: 5278-5281
- [c22]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi: A Flow Graph Technique for DFT Controller Modification. SoCC 2005: 55-60
- [c21]Hamid Reza Ghasemi, Zainalabedin Navabi: An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. VLSI Design 2005: 762-767
- 2004
- [j6]Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin: A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electronic Testing 20(2): 155-168 (2004)
- [j5]Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi: Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electronic Testing 20(6): 575-589 (2004)
- [j4]Farzin Karimi, Zainalabedin Navabi, Waleed Meleis, Fabrizio Lombardi: Using data compression in automatic test equipment for system-on-chip testing. IEEE T. Instrumentation and Measurement 53(2): 308-317 (2004)
- [c20]Bijan Alizadeh, Zainalabedin Navabi: Property Checking based on Hierarchical Integer Equations. ACSD 2004: 26-35
- [c19]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163
- [c18]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi: Instruction level test methodology for CPU core software-based self-testing. HLDVT 2004: 25-29
- [c17]Bijan Alizadeh, Zainalabedin Navabi: Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC 2004: 83-86
- 2003
- [c16]Ehsan Atoofian, Zainalabedin Navabi: A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium 2003: 84-89
- [c15]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Asian Test Symposium 2003: 274-277
- [c14]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi: Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications 2003: 139-143
- [c13]Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi: Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360
- [c12]Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi: Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38-
- [c11]Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi: Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. PDPTA 2003: 819-823
- [c10]Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi: Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186-
- [c9]Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi: Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
- [c8]Ehsan Atoofian, Zainalabedin Navabi: A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397
- 2002
- [c7]Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi: Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium 2002: 374-
- [c6]Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi: Data Compression for System-on-Chip Testing Using ATE. DFT 2002: 166-176
- 2001
- [c5]Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium 2001: 396-
- [c4]Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi: Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE 2001: 823
- [c3]Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie: An efficient BIST method for testing of embedded SRAMs. ISCAS (5) 2001: 73-76
1990 – 1999
- 1993
- [c2]Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai: Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. CHDL 1993: 569-586
- 1992
- [j3]Zainalabedin Navabi: A high-level language for design and modeling of hardware. Journal of Systems and Software 18(1): 5-18 (1992)
1980 – 1989
- 1984
- [j2]Fredrick J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud: Hardware Compilation from an RTL to a Storage Logic Array Target. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 208-217 (1984)
- 1981
- [j1]Fredrick J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi: Structure Specification with a Procedural Hardware Description Language. IEEE Trans. Computers 30(2): 157-161 (1981)
1970 – 1979
- 1979
- [c1]
Coauthor Index
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last updated on 2013-05-25 21:27 CEST by the dblp team