| 2012 | ||
|---|---|---|
| j2 | Mohammad Hossein Neishaburi, Zeljko Zilic: An infrastructure for debug using clusters of assertion-checkers. Microelectronics Reliability 52(11): 2781-2798 (2012) | |
| c20 | Mohammad Hossein Neishaburi, Zeljko Zilic: An enhanced debug-aware network interface for Network-on-Chip. ISQED 2012: 709-716 | |
| 2011 | ||
| c19 | Mohammad Hossein Neishaburi, Zeljko Zilic: Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. DFT 2011: 120-128 | |
| c18 | Mohammad Hossein Neishaburi, Zeljko Zilic: Debug Aware AXI-based Network Interface. DFT 2011: 399-407 | |
| c17 | Mohammad Hossein Neishaburi, Zeljko Zilic: A Fault Tolerant Hierarchical Network on Chip Router Architecture. DFT 2011: 445-453 | |
| c16 | Mohammad Hossein Neishaburi, Zeljko Zilic: On Failure Rate Assessment Using an Executable Model of the System. DSD 2011: 29-36 | |
| c15 | Mohammad Hossein Neishaburi, Zeljko Zilic: ERAVC: Enhanced reliability aware NoC router. ISQED 2011: 591-596 | |
| c14 | Mohammad Hossein Neishaburi, Zeljko Zilic: A distributed AXI-based platform for post-silicon validation. VTS 2011: 8-13 | |
| 2010 | ||
| c13 | Mohammad Hossein Neishaburi, Zeljko Zilic: Enabling efficient post-silicon debug by clustering of hardware-assertions. DATE 2010: 985-988 | |
| 2009 | ||
| c12 | Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Hossein Neishaburi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila, Hannu Tenhunen: An efficent dynamic multicast routing protocol for distributing traffic in NOCs. DATE 2009: 1064-1069 | |
| c11 | Mohammad Hossein Neishaburi, Zeljko Zilic: Reliability aware NoC router architecture using input channel buffer sharing. ACM Great Lakes Symposium on VLSI 2009: 511-516 | |
| 2008 | ||
| j1 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi: Graph based test case generation for TLM functional verification. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 288-295 (2008) | |
| 2007 | ||
| c10 | Mohammad Hossein Neishaburi, Masoud Daneshtalab, Majid Nabi, Siamak Mohammadi: System Level Voltage Scheduling Technique Using UML-RT Model. AICCSA 2007: 500-505 | |
| c9 | Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari: Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. AICCSA 2007: 528-534 | |
| c8 | Alireza Aminlou, Maryam Homayouni, Mohammad Hossein Neishaburi, Siamak Mohammadi: A Superior Low Complexity Rate Control Algorithm. AICCSA 2007: 726-729 | |
| c7 | Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250 | |
| c6 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi: Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. DSD 2007: 157-164 | |
| c5 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538 | |
| c4 | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206 | |
| c3 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari: Assertion based design error diagnosis for core-based SoCs. SoCC 2007: 269-272 | |
| c2 | Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, Mohammad Riazati, Ali Afzali-Kusha, Siamak Mohammadi: Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. VLSI Design 2007: 546-550 | |
| c1 | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi: A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248 | |
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