Nicola Nicolici

Phillip Kinsman, Nicola Nicolici: NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. IEEE Trans. Computers 62(3): 524-535 (2013)

Ho Fai Ko, Nicola Nicolici: Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61(11): 1563-1575 (2012)

Zahra Lak, Nicola Nicolici: On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1845-1856 (2012)

Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici: Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. VLSI Syst. 20(6): 1118-1131 (2012)

Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita: Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303

Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici: In-system constrained-random stimuli generation for post-silicon validation. ITC 2012: 1-10

George A. Constantinides, Nicola Nicolici: Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Design & Test of Computers 28(4): 6-7 (2011)

George A. Constantinides, Adam B. Kinsman, Nicola Nicolici: Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Design & Test of Computers 28(4): 8-17 (2011)

Adam B. Kinsman, Nicola Nicolici: Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. IEEE Trans. Computers 60(4): 498-507 (2011)

Ehab Anis Daoud, Nicola Nicolici: On Using Lossy Compression for Repeatable Experiments during Silicon Debug. IEEE Trans. Computers 60(7): 937-950 (2011)

Adam B. Kinsman, Nicola Nicolici: Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. IEEE Trans. Computers 60(11): 1652-1663 (2011)

Adam B. Kinsman, Nicola Nicolici: Automated Range and Precision Bit-Width Allocation for Iterative Computations. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1265-1278 (2011)

Jason Thong, Nicola Nicolici: An Optimal and Practical Approach to Single Constant Multiplication. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1373-1386 (2011)

Adam B. Kinsman, Nicola Nicolici: A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Trans. VLSI Syst. 19(3): 499-503 (2011)

Ehab Anis Daoud, Nicola Nicolici: Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. IEEE Trans. VLSI Syst. 19(4): 559-570 (2011)

Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici: Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. VLSI Syst. 19(8): 1380-1393 (2011)

Phillip Kinsman, Nicola Nicolici: Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. DAC 2011: 286-287

Zahra Lak, Nicola Nicolici: A New Algorithm for Post-Silicon Clock Measurement and Tuning. DFT 2011: 53-59

Zahra Lak, Nicola Nicolici: In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. ICCAD 2011: 434-441

Adam B. Kinsman, Nicola Nicolici: Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 405-413 (2010)

Ramin Mafi, Shahin Sirouspour, Behzad Mahdavikhah, Brian Moody, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici: A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies. IEEE T. Haptics 3(3): 211-223 (2010)

Adam B. Kinsman, Nicola Nicolici: Time-Multiplexed Compressed Test of SOC Designs. IEEE Trans. VLSI Syst. 18(8): 1159-1172 (2010)

Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici: Post-silicon validation opportunities, challenges and recent advances. DAC 2010: 12-17

Adam B. Kinsman, Nicola Nicolici: Robust design methods for hardware accelerators for iterative algorithms in scientific computing. DAC 2010: 254-257

Kaveh Elizeh, Nicola Nicolici: Embedded memory binding in FPGAs. DAC 2010: 457-462

Jason Thong, Nicola Nicolici: A novel optimal single constant multiplication algorithm. DAC 2010: 613-616

Ho Fai Ko, Nicola Nicolici: Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. European Test Symposium 2010: 62-67

Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici: Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. FPGA 2010: 189-198

Jason Thong, Nicola Nicolici: Combined optimal and heuristic approaches for multiple constant multiplication. ICCD 2010: 266-273

Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour: Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682

Ho Fai Ko, Nicola Nicolici: Automated trace signals selection using the RTL descriptions. ITC 2010: 144-153

Ho Fai Ko, Nicola Nicolici: Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 285-297 (2009)

Jason Thong, Nicola Nicolici: Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. IEEE Trans. VLSI Syst. 17(9): 1353-1357 (2009)

Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic: A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC 2009: 499-502

Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris: Automated data analysis solutions to silicon debug. DATE 2009: 982-987

Adam B. Kinsman, Nicola Nicolici: Finite Precision bit-width allocation using SAT-Modulo Theory. DATE 2009: 1106-1111

Ho Fai Ko, Nicola Nicolici: Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. European Test Symposium 2009: 17-22

Nicola Nicolici, Ho Fai Ko: Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT 2009: 172-175

Adam B. Kinsman, Nicola Nicolici: Computational bit-width allocation for operations in vector calculus. ICCD 2009: 433-438

Nicola Nicolici, Patrick Girard: Guest Editorial. J. Electronic Testing 24(4): 325-326 (2008)

Ho Fai Ko, Nicola Nicolici: Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electronic Testing 24(4): 393-403 (2008)

Ho Fai Ko, Nicola Nicolici: Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2092-2097 (2008)

Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008

Ho Fai Ko, Nicola Nicolici: On Automated Trigger Event Generation in Post-Silicon Validation. DATE 2008: 256-259

Ho Fai Ko, Nicola Nicolici: Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE 2008: 1298-1303

Ehab Anis Daoud, Nicola Nicolici: On Bypassing Blocking Bugs during Post-Silicon Validation. European Test Symposium 2008: 69-74

Ramin Mafi, Shahin Sirouspour, Brian Moody, Behzad Mahdavikhah, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill: Hardware-based parallel computing for real-time haptic rendering of deformable objects. IROS 2008: 4187

Ho Fai Ko, Nicola Nicolici: A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED 2008: 649-654

Adam B. Kinsman, Nicola Nicolici: Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ISQED 2008: 832-837

Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici: Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC 2008: 1-10

Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici: DATE 07 workshop on diagnostic services in NoCs. IEEE Design & Test of Computers 24(5): 510 (2007)

Erik Jan Marinissen, Nicola Nicolici: Editorial Silicon Debug and Diagnosis. IET Computers & Digital Techniques 1(6): 659-660 (2007)

Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007)

Ehab Anis, Nicola Nicolici: Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. DATE 2007: 225-230

Nicola Nicolici, Xiaoqing Wen: Embedded Tutorial on Low Power Test. European Test Symposium 2007: 202-210

Ehab Anis, Nicola Nicolici: On using lossless compression of debug data in embedded logic analysis. ITC 2007: 1-10

Qiang Xu, Nicola Nicolici: DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55(4): 470-485 (2006)

Qiang Xu, Nicola Nicolici: Multifrequency TAM design for hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 181-196 (2006)

Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici: Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. IEEE Trans. VLSI Syst. 14(5): 537-548 (2006)

Ho Fai Ko, Nicola Nicolici: RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD 2006

Qiang Xu, Nicola Nicolici: Modular SOC testing with reduced wrapper count. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1894-1908 (2005)

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Synchronization overhead in SOC compressed test. IEEE Trans. VLSI Syst. 13(1): 140-152 (2005)

Qiang Xu, Nicola Nicolici: Wrapper design for multifrequency IP cores. IEEE Trans. VLSI Syst. 13(6): 678-685 (2005)

Qiang Xu, Nicola Nicolici: Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. VLSI Syst. 13(11): 1275-1285 (2005)

Ho Fai Ko, Qiang Xu, Nicola Nicolici: Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175

Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC 2005: 123-128

Qiang Xu, Nicola Nicolici: On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. ITC 2005: 10

Nicola Nicolici, Bashir M. Al-Hashimi: Testability Trade-Offs for BIST Data Paths. J. Electronic Testing 20(2): 169-179 (2004)

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1142-1153 (2004)

Qiang Xu, Nicola Nicolici: Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium 2004: 2-7

Ho Fai Ko, Nicola Nicolici: Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium 2004: 454-459

Qiang Xu, Nicola Nicolici: Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE 2004: 416-421

Ho Fai Ko, Nicola Nicolici: Functional Illinois Scan Design at RTL. ICCD 2004: 78-81

Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici: Compressed Embedded Diagnosis of Logic Cores. ICCD 2004: 534-539

Qiang Xu, Nicola Nicolici: Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC 2004: 1196-1202

Nicola Nicolici, Bashir M. Al-Hashimi: Power-Conscious Test Synthesis and Scheduling. IEEE Design & Test of Computers 20(4): 48-55 (2003)

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 783-796 (2003)

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Addressing useless test data in core-based system-on-a-chip test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1568-1580 (2003)

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Test Data Compression: The System Integrator's Perspective. DATE 2003: 10726-10731

Qiang Xu, Nicola Nicolici: Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE 2003: 10744-10752

Bai Hong Fang, Nicola Nicolici: Power-Constrained Embedded Memory BIST Architecture. DFT 2003: 451-458

Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici: Embedded Compact Deterministic Test for IP-Protected Cores. DFT 2003: 519-

Bai Hong Fang, Qiang Xu, Nicola Nicolici: Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD 2003: 599-606

Qiang Xu, Nicola Nicolici: On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC 2003: 622-631

Nicola Nicolici, Bashir M. Al-Hashimi: Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. IEEE Trans. Computers 51(6): 721-734 (2002)

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1217-1225 (2002)

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. DATE 2002: 604-611

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Scan Architecture for Shift and Capture Cycle Power Reduction. DFT 2002: 129-137

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. ICCD 2002: 474-479

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. ITC 2002: 64-73

Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici: Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. VTS 2002: 423-432

Nicola Nicolici, Bashir M. Al-Hashimi: Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. DATE 2001: 802

Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Power constrained test scheduling using power profile manipulation. ISCAS (5) 2001: 251-254

Nicola Nicolici, Bashir M. Al-Hashimi: Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. ITC 2001: 72-81

Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams: BIST hardware synthesis for RTL data paths based on testcompatibility classes. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1375-1385 (2000)

Nicola Nicolici, Bashir M. Al-Hashimi: Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. DATE 2000: 715-722

Nicola Nicolici, Bashir M. Al-Hashimi: Power conscious test synthesis and scheduling for BIST RTL data paths. ITC 2000: 662-671

Nicola Nicolici, Bashir M. Al-Hashimi: Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. DATE 1999: 289-

Nicola Nicolici, Bashir M. Al-Hashimi: Correction to the Proof of Theorem 2 in ``Parallel Signature Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 47(12): 1426 (1998)