Hiroaki Nishi

Junichi Sawada, Hiroaki Nishi: Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. FPL 2012: 499-502

Tianmeng Shen, Toshiro Togoshi, Hiroaki Nishi: Implementation and substantiation of energy management systems for terminal buildings. ETFA 2011: 1-4

Akihiro Oda, Hiroaki Nishi: Self-Organized Link State Aware Routing for Multiple Mobile Agents in Wireless Network. IEICE Transactions 93-B(8): 2012-2021 (2010)

Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi: A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet. ICPP Workshops 2010: 82-88

Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi: Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet. PDPTA 2010: 402-407

Hiroyuki Tanaka, Kouhei Ohnishi, Hiroaki Nishi, Toshikazu Kawai, Yasuhide Morikawa, Soji Ozawa, Toshiharu Furukawa: Implementation of Bilateral Control System Based on Acceleration Control Using FPGA for Multi-DOF Haptic Endoscopic Surgery Robot. IEEE Transactions on Industrial Electronics 56(3): 618-627 (2009)

Eijirou Ohashi, Takahiro Aiko, Toshiaki Tsuji, Hiroaki Nishi, Kouhei Ohnishi: Collision Avoidance Method of Humanoid Robot With Arm Force. IEEE Transactions on Industrial Electronics 54(3): 1632-1641 (2007)

Ena Ishii, Hiroaki Nishi, Kouhei Ohnishi: Improvement of Performances in Bilateral Teleoperation by Using FPGA. IEEE Transactions on Industrial Electronics 54(4): 1876-1884 (2007)

Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano: Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distrib. Syst. 18(9): 1282-1295 (2007)

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi: 100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet. IEICE Transactions 89-B(3): 696-703 (2006)

Michitaka Okuno, Shinji Nishimura, Shin-ichi Ishida, Hiroaki Nishi: Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic. IEICE Transactions 89-C(11): 1620-1628 (2006)

Michitaka Okuno, Shin-ichi Ishida, Hiroaki Nishi: Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router. IEICE Transactions 88-C(4): 536-543 (2005)

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi: A 100-Gb-Ethernet subsystem for next-generation metro-area network. ICC 2005: 1036-1042

Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467

Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada: Design methodology for SoC arthitectures based on reusable virtual cores. ASP-DAC 2004: 256-262

Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano: Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. Applied Informatics 2003: 738-743

Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida: VCore-based design methodology. ASP-DAC 2003: 441-445

Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada: Synthesis for SoC architecture using VCores. ASP-DAC 2003: 446-452

Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh: Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. CCGRID 2003: 318-325

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Cluster Computing 5(1): 7-17 (2002)

Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano: A network switch for supporting high-performance parallel processing by computers distributed in local areas. Systems and Computers in Japan 32(14): 24-33 (2001)

Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi: Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001)

Shinji Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano: RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Generation Comput. 18(2): 187-197 (2000)

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16

Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. HPDC 2000: 296-297

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194

Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh: The RDT network router chip. ASP-DAC 1997: 675-676