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Shinji Nishimura
2010 – today
- 2012
[j7]Masashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura: A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology. IEICE Transactions 95-B(11): 3437-3444 (2012)- 2011
- [j6]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura: A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. J. Solid-State Circuits 46(12): 3101-3112 (2011)
- [c6]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura: 10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150
- 2010
- [j5]Hidehiro Toyoda, Goichi Ono, Shinji Nishimura: 100GbE PHY and MAC layer implementations. IEEE Communications Magazine 48(3) (2010)
- [c5]Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura: A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. CICC 2010: 1-4
2000 – 2009
- 2008
- [c4]Hidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada: A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet. ICC 2008: 5417-5421
- [c3]Masaki Yamada, Takeki Yazaki, Shinji Nishimura, Naoya Ikeda: Technologies to Save Power for Carrier Class Routers and Switches. SAINT 2008: 385-388
- 2007
- [j4]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada: A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications. IEICE Transactions 90-C(10): 1957-1963 (2007)
- [c2]Takashi Ishikawa, Seishi Hanaoka, Mikio Kataoka, Masashi Yano, Shinji Nishimura: Basic Simulation Result of Inter System Handover for Cognitive Radio. FGCN (2) 2007: 270-273
- 2006
- [j3]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi: 100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet. IEICE Transactions 89-B(3): 696-703 (2006)
- [j2]Michitaka Okuno, Shinji Nishimura, Shin-ichi Ishida, Hiroaki Nishi: Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic. IEICE Transactions 89-C(11): 1620-1628 (2006)
- 2005
- [c1]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi: A 100-Gb-Ethernet subsystem for next-generation metro-area network. ICC 2005: 1036-1042
- 2000
- [j1]Shinji Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano: RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Generation Comput. 18(2): 187-197 (2000)
Coauthor Index
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last updated on 2013-03-02 19:22 CET by the dblp team