| 2004 | ||
|---|---|---|
| c9 | Charles Njinda: A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. ITC 2004: 1061-1071 | |
| 1997 | ||
| c8 | Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh: Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC 1997: 95-100 | |
| c7 | Rajesh Raina, Charles Njinda, Robert F. Molyneaux: How Seriously Do You Take Your Possible-Detect Faults? ITC 1997: 819-828 | |
| 1995 | ||
| c6 | ||
| 1994 | ||
| j2 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994) | |
| c5 | Ishwar Parulkar, Melvin A. Breuer, Charles Njinda: Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC 1994: 345-356 | |
| 1993 | ||
| j1 | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer: Generating a family of testable designs using the BILBO methodology. J. Electronic Testing 4(1): 71-89 (1993) | |
| 1992 | ||
| c4 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29 | |
| c3 | Sridhar Narayanan, Charles Njinda, Melvin A. Breuer: Optimal Sequencing of Scan Registers. ITC 1992: 293-302 | |
| 1991 | ||
| c2 | Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer: Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD 1991: 236-239 | |
| c1 | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer: A Systematic Approach for Designing Testable VLSI Circuits. ICCAD 1991: 496-499 | |
| 1 | Robert Bailey | |
| 2 | Charlie Beh | |
| 3 | Melvin A. Breuer | |
| 4 | Neeraj Kaul | |
| 5 | Kuen-Jong Lee | |
| 6 | Sen-Pin Lin | |
| 7 | Robert F. Molyneaux | |
| 8 | Debaditya Mukherjee | |
| 9 | Sridhar Narayanan | |
| 10 | Ishwar Parulkar | |
| 11 | Rajesh Raina |
Colors in the list of coauthors
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