Koichi Nose

Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno: A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. J. Solid-State Circuits 47(4): 832-840 (2012)

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda: An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. J. Solid-State Circuits 45(10): 2057-2065 (2010)

Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno: A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC 2010: 192-193

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno: Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471

Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi: LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Transactions 91-C(2): 131-137 (2008)

Koichi Nose, Takayasu Sakurai: Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29

Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai: Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286

Koichi Nose, Takayasu Sakurai: Analysis and future trend of short-circuit power. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1023-1030 (2000)

Koichi Nose, Takayasu Sakurai: Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474

Koichi Nose, Soo-Ik Chae, Takayasu Sakurai: Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230

Koichi Nose, Takayasu Sakurai: Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326