Altan Odabasioglu

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	2002
j2		Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: An analysis of the wire-load model uncertainty problem. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002)
	2001
c4		Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: Overcoming wireload model uncertainty during physical design. ISPD 2001: 182-189
	1999
c3		Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63
c2		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: Practical considerations for passive reduction of RLC circuits. ICCAD 1999: 214-220
	1998
j1		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 645-654 (1998)
	1997
c1		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD 1997: 58-65

Coauthor Index

1	Emrah Acar	[c3]
2	Mustafa Celik	[c3] [c2] [j1] [c1]
3	Padmini Gopalakrishnan	[j2] [c4]
4	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[j2] [c4] [c3] [c2] [j1] [c1]
5	Salil Raje	[j2] [c4]

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