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 | 2012 | |
|---|---|---|
| c9 |      | Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu: Real-time testing method for 16 Gbps 4-PAM signal interface. ITC 2012: 1-10 |
| 2011 | ||
| c8 | | Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu: Real-time testing method for 16 Gbps 4-PAM signal interface. ITC 2011: 1-10 |
| 2009 | ||
| c7 | | Daisuke Watanabe, Atsushi Ono, Toshiyuki Okayasu: CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission. ISSCC 2009: 106-107 |
| c6 | | Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu: Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing. ITC 2009: 1-10 |
| 2006 | ||
| c5 | | Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka: Multi Strobe Circuit for 2.133GHz Memory Test System. ITC 2006: 1-9 |
| 2005 | ||
| c4 | | Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe: CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system. ITC 2005: 9 |
| 2004 | ||
| c3 | | Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu: 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ITC 2004: 1255-1262 |
| 2002 | ||
| c2 | | Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto: CMOS Circuit Technology for Precise GHz Timing Generator. ITC 2002: 894-902 |
| 1994 | ||
| c1 | | Takashi Sekino, Toshiyuki Okayasu: Ultra Hi-Speed Pin-Electronics and Test Station Using GaAs IC. ITC 1994: 683-690 |
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