Shunsuke Okumura

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Transactions 96-C(4): 528-537 (2013)

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC 2013: 79-80

Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Transactions 95-C(4): 572-578 (2012)

Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi: A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Transactions 95-C(4): 579-585 (2012)

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi: Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Transactions 95-A(8): 1359-1365 (2012)

Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Transactions 95-C(10): 1675-1681 (2012)

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Transactions 95-A(12): 2226-2233 (2012)

Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90

Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492

Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519

Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Transactions 94-A(12): 2693-2700 (2011)

Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4

Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10^-19. ESSCIRC 2011: 527-530

Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527

Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi: 0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED 2011: 219-222

Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto: Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325

Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4

Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Dependable SRAM with 7T/14T Memory Cells. IEICE Transactions 92-C(4): 423-432 (2009)

Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300

Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008)

Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102