Michael Orshansky

Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan: An accurate sparse-matrix based framework for statistical static timing analysis. Integration 45(4): 365-375 (2012)

Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis, Michael Orshansky: Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. IEEE Trans. on CAD of Integrated Circuits and Systems 31(10): 1485-1498 (2012)

Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky: Modeling and synthesis of quality-energy optimal approximate adders. ICCAD 2012: 728-735

Kareem Ragab, Ranjit Gharpurey, Michael Orshansky: Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation. ISQED 2012: 143-150

Mukund Kalyanaraman, Michael Orshansky: Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation. IACR Cryptology ePrint Archive 2012: 413 (2012)

Ku He, Andreas Gerstlauer, Michael Orshansky: Controlled timing-error acceptance for low energy IDCT design. DATE 2011: 758-763

Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky: Coupling timing objectives with optical proximity correction for improved timing yield. ISQED 2011: 97-102

Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky: Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. CICC 2010: 1-4

Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky: A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278

Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky: An algorithm for exploiting modeling error statistics to enable robust analog optimization. ICCAD 2010: 62-69

Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky: SMATO: Simultaneous mask and target optimization for improving lithographic process window. ICCAD 2010: 100-106

Mehmet Basoglu, Michael Orshansky, Mattan Erez: NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. ISLPED 2010: 253-258

Michael Orshansky, Wei-Shen Wang: Statistical analysis of circuit timing using majorization. Commun. ACM 52(8): 95-100 (2009)

Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky: Mitigation of intra-array SRAM variability using adaptive voltage architecture. ICCAD 2009: 637-644

Michael Orshansky, Sani R. Nassif, Duane S. Boning: Design for Manufacturability and Statistical Design - A Constructive Approach. Series on integrated circuits and systems, Springer 2008, isbn 978-0-387-30928-6, pp. I-XIV, 1-310

Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey: The Search for Alternative Computational Paradigms. IEEE Design & Test of Computers 25(4): 334-343 (2008)

Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky: Electrically driven optical proximity correction based on linear programming. ICCAD 2008: 473-479

Bin Zhang, Michael Orshansky: Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ISQED 2008: 774-779

Wei-Shen Wang, Michael Orshansky: Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electronics 3(1): 1-12 (2007)

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky: Architecting a reliable CMP switch architecture. TACO 4(1) (2007)

Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan: A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1790-1802 (2007)

Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153

Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66

Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky: Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies. CoRR abs/cs/0703102 (2007)

Wei-Shen Wang, Michael Liu, Michael Orshansky: Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electronics 2(1): 1-7 (2006)

Wei-Shen Wang, Michael Orshansky: Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2976-2988 (2006)

Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky: Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC 2006: 161-166

Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527

Joonsoo Kim, Michael Orshansky: Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI 2006: 229-234

Murari Mani, Mahesh Sharma, Michael Orshansky: Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI 2006: 372-375

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky: BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16

Murari Mani, Ashish Kumar Singh, Michael Orshansky: Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD 2006: 19-26

Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236

Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky: Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322

Wei-Shen Wang, Michael Orshansky: Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD 2006: 884-890

Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5

Bin Zhang, Wei-Shen Wang, Michael Orshansky: FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED 2006: 755-760

Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang: Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC 2006: 1645-1649

Murari Mani, Anirudh Devgan, Michael Orshansky: An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314

Ashish Kumar Singh, Murari Mani, Michael Orshansky: Statistical technology mapping for parametric yield. ICCAD 2005: 511-518

Michael Orshansky, Arnab Bandyopadhyay: Fast statistical timing analysis handling arbitrary delay correlations. DAC 2004: 337-342

Murari Mani, Michael Orshansky: A New Statistical Optimization Algorithm for Gate Sizing. ICCD 2004: 272-277

Michael Liu, Wei-Shen Wang, Michael Orshansky: Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED 2004: 2-7

David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer: Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163

Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)

Michael Orshansky, Kurt Keutzer: A general probabilistic framework for worst case timing analysis. DAC 2002: 556-561

Kurt Keutzer, Michael Orshansky: From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 37-41

Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67

Michael Orshansky, James C. Chen, Chenming Hu: A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407