Yuji Osaki

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. J. Solid-State Circuits 47(7): 1776-1783 (2012)

Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi: A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC 2012: 69-72

Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa: Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Transactions 94-C(1): 80-88 (2011)

Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa: Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Transactions 94-C(6): 1042-1048 (2011)

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC 2011: 113-114

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202