DBLP: Jin Ouyang

	2011
j1		Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie: Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Foundations and Trends in Electronic Design Automation 5(1-2): 1-151 (2011)
c10		Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie: A frequent-value based PRAM memory architecture. ASP-DAC 2011: 211-216
c9		Jin Ouyang, Yuan Xie: Enabling quality-of-service in nanophotonic network-on-chip. ASP-DAC 2011: 351-356
c8		Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu: F²BFLY: an on-chip free-space optical network with wavelength-switching. ICS 2011: 348-358
	2010
c7		Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie: Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD 2010: 477-482
c6		Jin Ouyang, Yuan Xie: LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. MICRO 2010: 409-420
	2009
c5		Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin: Arithmetic unit design using 180nm TSV-based 3D stacking technology. 3DIC 2009: 1-4
c4		Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie: 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC 2009: 1-6
c3		Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller: CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES 2009: 175-184
	2008
c2		Yibo Chen, Jin Ouyang, Yuan Xie: ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30
c1		Jin Ouyang, Yuan Xie: Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214

2011

Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie: Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Foundations and Trends in Electronic Design Automation 5(1-2): 1-151 (2011)

c10

Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie: A frequent-value based PRAM memory architecture. ASP-DAC 2011: 211-216

Jin Ouyang, Yuan Xie: Enabling quality-of-service in nanophotonic network-on-chip. ASP-DAC 2011: 351-356

Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu: F²BFLY: an on-chip free-space optical network with wavelength-switching. ICS 2011: 348-358

2010

Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie: Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. ICCAD 2010: 477-482

Jin Ouyang, Yuan Xie: LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support. MICRO 2010: 409-420

2009

Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin: Arithmetic unit design using 180nm TSV-based 3D stacking technology. 3DIC 2009: 1-4

Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie: 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC 2009: 1-6

Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller: CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. CASES 2009: 175-184

2008

Yibo Chen, Jin Ouyang, Yuan Xie: ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30

Jin Ouyang, Yuan Xie: Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214

1	Yibo Chen	[j1] [c5] [c2]
2	Xiangyu Dong	[j1]
3	Lian Duan	[c5] [c4]
4	Mo Kwai Hung	[c4]
5	Mary Jane Irwin	[c5]
6	Zhiwen Liu	[c8]
7	Sibin Mohan	[c3]
8	Frank Mueller	[c3]
9	Dimin Niu	[c10] [c8]
10	Matthew Poremba	[c7]
11	Raghuveer Raghavendra	[c3]
12	Guangyu Sun	[j1] [c10] [c5]
13	Jing Xie	[c7]
14	Yuan Xie	[j1] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
15	Jiang Xu	[c4]
16	Chuan Yang	[c8]
17	Yaoyao Ye	[c4]
18	Tao Zhang	[c5] [c3]

Jin Ouyang

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