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 | 2005 | |
|---|---|---|
| c9 |      | Yuichiro Hourai, Akira Nishida, Yoshio Oyanagi: Network-aware Data mMapping on Parallel Molecular Dynamicas. ICPADS (1) 2005: 126-132 |
| 2004 | ||
| e1 |  | Suresh Manandhar, Jim Austin, Uday B. Desai, Yoshio Oyanagi, Asoke K. Talukder (Eds.): Applied Computing, Second Asian Applied Computing Conference, AACC 2004, Kathmandu, Nepal, October 29-31, 2004. Proceedings. Lecture Notes in Computer Science 3285, Springer 2004, isbn 3-540-23659-7 |
| 2003 | ||
| c8 | | Akira Nishida, Yoshio Oyanagi: Performance Evaluation of Low Level Multithreaded BLAS Kernels on Intel Processor Based cc-NUMA Systems. ISHPC 2003: 500-510 |
| 2001 | ||
| c7 | | Shoji Itoh, Yoshio Oyanagi, Shao-Liang Zhang, Makoto Natori: Parallel Aspect of Block Preconditioning with the Splitting Correction. PPSC 2001 |
| 1999 | ||
| j2 | | Reiji Suda, Akira Nishida, Yoshio Oyanagi: A high performance parallelization scheme for the Hessenberg double shift QR algorithm. Parallel Computing 25(6): 729-744 (1999) |
| j1 | | Yoshio Oyanagi: Development of supercomputers in Japan: Hardware and software. Parallel Computing 25(13-14): 1545-1567 (1999) |
| 1998 | ||
| c6 | | Reiji Suda, Yoshio Oyanagi: The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis. ASP-DAC 1998: 507-512 |
| 1995 | ||
| c5 | | Reiji Suda, Yoshio Oyanagi: Implementation of Sparta, a Highly Parallel Circuit Simulator by the Preconditioned Jacobi Method, on a Distributed Memory Machine. International Conference on Supercomputing 1995: 209-217 |
| 1994 | ||
| c4 | | Osamu Tatebe, Yoshio Oyanagi: Efficient implementation of the multigrid preconditioned conjugate gradient method on distributed memory machines. SC 1994: 194-203 |
| 1989 | ||
| c3 | | Tomonori Shirakawa, Takeshi Hoshino, Yoshio Oyanagi, Yohei Iwasaki, T. Yoshié: QCDPAX-an MIMD array of vector processors for the numerical simulation of quantum chromodynamics. SC 1989: 495-504 |
| 1984 | ||
| c2 | | Tsutomu Hoshino, Tomonori Shirakawa, Yoshio Oyanagi, Kiyo Takenouchi, Toshio Kawai: Super Freedom Simulator PAX. VLSI Engineering 1984: 39-51 |
| 1983 | ||
| c1 | | Tsutomu Hoshino, Tomonori Shirakawa, Takeshi Kamimura, Takahisa Kageyama, Kiyo Takenouchi, Hidehiko Abe, Satoshi Sekiguchi, Yoshio Oyanagi, Toshio Kawai: Highly Parallel Processor Array "PAX" for Wide Scientific Applications. ICPP 1983: 95-105 |
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