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 | 2013 | |
|---|---|---|
| j22 |      | Xiaohang Wang, Peng Liu, Mei Yang, Maurizio Palesi, Yingtao Jiang, Michael C. Huang: Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip. J. Comput. Sci. Technol. 28(1): 54-71 (2013) |
| 2012 | ||
| j21 | | Rafael Tornero, Maurizio Palesi, José Duato: A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip. Computing and Informatics 31(5): 939-970 (2012) |
| j20 | | Fangyang Shen, Mei Yang, Maurizio Palesi: Guest Editors' Introduction to the Special Issue on "Emerging Computing Architectures and Systems". Computers & Electrical Engineering 38(3): 722-723 (2012) |
| j19 | | Maurizio Palesi, Rafael Tornero, Juan Manuel Orduña, Vincenzo Catania, Daniela Panno: Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach. J. UCS 18(7): 937-969 (2012) |
| j18 | | Davide Patti, Andrea Spadaccini, Maurizio Palesi, Fabrizio Fazzino, Vincenzo Catania: Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator. IEEE Trans. Education 55(3): 406-411 (2012) |
| j17 | | Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi: Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distrib. Syst. 23(7): 1205-1215 (2012) |
| 2011 | ||
| j16 | | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11(1): 382-398 (2011) |
| j15 | | Maurizio Palesi, Shashi Kumar, Radu Marculescu: Network-on-chip architectures and design methodologies. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 83-84 (2011) |
| j14 | | Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania: Data Encoding Schemes in Networks on Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 774-786 (2011) |
| c37 | | Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi: Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502 |
| c36 | | Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu: Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip. NPC 2011: 232-247 |
| c35 | | Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu: Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. VLSI-SoC 2011: 337-342 |
| 2010 | ||
| j13 | | Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 426-440 (2010) |
| c34 | | Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania: An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD 2010: 37-44 |
| c33 | | Rickard Holsmark, Shashi Kumar, Maurizio Palesi: A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. Euro-Par Workshops 2010: 153-161 |
| 2009 | ||
| j12 | | Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Bandwidth-aware routing algorithms for networks-on-chip platforms. IET Computers & Digital Techniques 3(5): 413-429 (2009) |
| j11 | | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009) |
| j10 | | Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato: Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. VLSI Syst. 17(3): 356-369 (2009) |
| c32 | | Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania: Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD 2009: 119-126 |
| c31 | | Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales: An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. DSD 2009: 643-650 |
| c30 | | Rafael Tornero, Valentino Sterrantino, Maurizio Palesi, Juan M. Orduña: A multi-objective strategy for concurrent mapping and routing in networks on chip. IPDPS 2009: 1-8 |
| c29 | | Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia: HiRA: A methodology for deadlock free routing in hierarchical networks on chip. NOCS 2009: 2-11 |
| 2008 | ||
| j9 | | Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 427-440 (2008) |
| j8 | | Vincenzo Catania, Maurizio Palesi, Davide Patti: Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. TACO 5(2) (2008) |
| j7 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008) |
| c28 | | Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. DSD 2008: 18-25 |
| c27 | | Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: High Performance Computing for Embedded System Design: A Case Study. DSD 2008: 656-659 |
| c26 | | Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato: A Communication-Aware Topological Mapping Technique for NoCs. Euro-Par 2008: 910-919 |
| c25 | | Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106 |
| 2007 | ||
| j6 | | Vincenzo Catania, Maurizio Palesi, Davide Patti: Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. Journal of Circuits, Systems, and Computers 16(5): 819-846 (2007) |
| j5 | | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Efficient design space exploration for application specific systems-on-a-chip. Journal of Systems Architecture 53(10): 733-750 (2007) |
| j4 | | Davide Bertozzi, Shashi Kumar, Maurizio Palesi: Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design 2007 (2007) |
| c24 | | Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania: Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE 2007: 1-6 |
| c23 | | Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania: Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8 |
| 2006 | ||
| j3 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. UCS 12(4): 370-394 (2006) |
| c22 | | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147 |
| c21 | | Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania: Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228 |
| c20 | | Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006: 696-703 |
| c19 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTImedia 2006: 79-84 |
| c18 | | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122 |
| c17 | | Maurizio Palesi, Shashi Kumar, Rickard Holsmark: A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS 2006: 373-384 |
| c16 | | Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Hybrid Soft Computing Approach for Automated Computer Design. STAIRS 2006: 84-95 |
| 2005 | ||
| j2 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 635-645 (2005) |
| c15 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91 |
| c14 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943 |
| c13 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119 |
| c12 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093 |
| 2004 | ||
| j1 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evolutionary Computation 8(4): 329-346 (2004) |
| c11 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187 |
| c10 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198 |
| 2003 | ||
| c9 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation (1) 2003: 107-114 |
| c8 |  | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTImedia 2003: 65-72 |
| c7 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81 |
| c6 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30 |
| c5 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431 |
| 2002 | ||
| c4 | | Maurizio Palesi, Tony Givargis: Multi-objective design space exploration using genetic algorithms. CODES 2002: 67-72 |
| c3 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Framework for Design Space Exploration of Parameterized VLSI Systems. VLSI Design 2002: 245-250 |
| 2001 | ||
| c2 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Parameterised system design based on genetic algorithms. CODES 2001: 177-182 |
| c1 | | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168 |
Colors in the list of coauthors
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