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Gaetano Palumbo
2010 – today
- 2012
[j34]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. on Circuits and Systems 59-I(1): 159-169 (2012)- [j33]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale: Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators. IEEE Trans. on Circuits and Systems 59-I(9): 1880-1893 (2012)
- [j32]Gaetano Palumbo, Melita Pennisi, Massimo Alioto: A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates. IEEE Trans. on Circuits and Systems 59-I(10): 2292-2300 (2012)
- [j31]Elio Consoli, Gaetano Palumbo, Melita Pennisi: Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. IEEE Trans. VLSI Syst. 20(2): 284-295 (2012)
- [c71]Massimo Alioto, Gaetano Palumbo, Melita Pennisi: A simple keeper topology to reduce delay variations in nanometer domino logic. ISCAS 2012: 1576-1579
- [c70]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253
- [c69]Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey: Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484
- 2011
- [j30]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Optimized design of parallel carry-select adders. Integration 44(1): 62-74 (2011)
- [j29]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. VLSI Syst. 19(5): 725-736 (2011)
- [j28]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. VLSI Syst. 19(5): 737-750 (2011)
- [c68]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD 2011: 512-515
- [c67]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: An ultra-compact MOS model in nanometer technologies. ECCTD 2011: 520-523
- [c66]Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal: Figures of merit for class AB input stages. ECCTD 2011: 749-752
- [c65]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. ISCAS 2011: 29-32
- [c64]Elio Consoli, Gaetano Palumbo, Melita Pennisi: TG Master-Slave FFs: High-speed optimization. ISCAS 2011: 554-557
- [c63]Massimo Alioto, Elio Consoli, Gaetano Palumbo: DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566
- [c62]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo: Verilog-A modeling of SPAD statistical phenomena. ISCAS 2011: 773-776
- 2010
- [j27]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads. IET Circuits, Devices & Systems 4(2): 87-98 (2010)
- [j26]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications. Journal of Circuits, Systems, and Computers 19(2): 325-334 (2010)
- [j25]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. on Circuits and Systems 57-I(6): 1273-1286 (2010)
- [j24]Massimo Alioto, Elio Consoli, Gaetano Palumbo: General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. on Circuits and Systems 57-I(7): 1583-1596 (2010)
- [j23]Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. IEEE Trans. VLSI Syst. 18(5): 697-710 (2010)
- [c61]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324
- [c60]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. ISCAS 2010: 777-780
- [c59]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. ISCAS 2010: 2816-2819
- [c58]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. ISCAS 2010: 2832-2835
- [c57]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72
2000 – 2009
- 2009
- [j22]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi: Approach to analyse and design nearly sinusoidal oscillators. IET Circuits, Devices & Systems 3(4): 204-221 (2009)
- [j21]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers. Journal of Circuits, Systems, and Computers 18(7): 1321-1331 (2009)
- [j20]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Analysis and Modeling of Energy Consumption in RLC Tree Circuits. IEEE Trans. VLSI Syst. 17(2): 278 (2009)
- [c56]Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Analysis of the impact of random process variations in CMOS tapered buffers. ICECS 2009: 57-60
- [c55]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs. ICECS 2009: 128-131
- [c54]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: A high-speed low-power output buffer amplifier for large-size LCD applications. ICECS 2009: 132-135
- [c53]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi: Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity. ICECS 2009: 155-158
- [c52]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. ICECS 2009: 275-278
- [c51]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications. ISCAS 2009: 1949-1952
- [c50]Davide Marano, Gaetano Palumbo, Salvatore Pennisi: A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers. ISCAS 2009: 2725-2728
- [c49]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. ISCAS 2009: 3150-3153
- 2008
- [j19]Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica: Accurate model for single-photon avalanche diodes. IET Circuits, Devices & Systems 2(2): 207-212 (2008)
- [j18]Walter Aloisi, Gaetano Palumbo, Salvatore Pennisi: Design methodology of Miller frequency compensation with current buffer/amplifier. IET Circuits, Devices & Systems 2(2): 227-233 (2008)
- [j17]Gaetano Palumbo, Melita Pennisi: AMOLED pixel driver circuits based on poly-Si TFTs: A comparison. Integration 41(3): 439-446 (2008)
- [j16]Massimo Alioto, Gaetano Palumbo: Power-Aware Design of Nanometer MCML Tapered Buffers. IEEE Trans. on Circuits and Systems 55-II(1): 16-20 (2008)
- [j15]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi: Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion. IEEE Trans. on Circuits and Systems 55-II(7): 628-632 (2008)
- [j14]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi: Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier. IEEE Trans. on Circuits and Systems 55-II(10): 991-995 (2008)
- [j13]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi: Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs. IEEE Trans. on Circuits and Systems 55-II(11): 1099-1103 (2008)
- [j12]Rosario Mita, Gaetano Palumbo: High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes. IEEE T. Instrumentation and Measurement 57(3): 543-547 (2008)
- [c48]Massimo Alioto, Gaetano Palumbo: Power-delay optimization in MCML tapered buffers. ISCAS 2008: 141-144
- [c47]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale: Low-voltage LDO Compensation Strategy based on Current Amplifiers. ISCAS 2008: 2681-2684
- [c46]Massimo Alioto, Massimo Poli, Gaetano Palumbo: Explicit energy evaluation in RLC tree circuits with ramp inputs. ISCAS 2008: 2865-2868
- [c45]Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. PATMOS 2008: 136-145
- 2007
- [j11]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal 38(1): 130-139 (2007)
- [c44]Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo: Rosenstark-like Representation of Feedback Amplifier Resistance. ISCAS 2007: 2212-2215
- [c43]Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi: Miller Compensation: Optimization with Current Buffer/Amplifier. ISCAS 2007: 2216-2219
- [c42]Massimo Alioto, Gaetano Palumbo: High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ISCAS 2007: 2998-3001
- [c41]Massimo Alioto, Gaetano Palumbo: Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ISCAS 2007: 3255-3258
- [c40]Massimo Alioto, Gaetano Palumbo: Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ISCAS 2007: 3732-3735
- 2006
- [j10]Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica: A fast driver circuit for single-photon sensors. Microelectronics Journal 37(10): 1092-1096 (2006)
- [j9]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits. IEEE Trans. VLSI Syst. 14(5): 452-461 (2006)
- [j8]Massimo Alioto, Gaetano Palumbo: Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. VLSI Syst. 14(12): 1322-1335 (2006)
- [c39]Massimo Alioto, Gaetano Palumbo: Delay uncertainty due to supply variations in static and dynamic full adders. ISCAS 2006
- [c38]
- [c37]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ISCAS 2006
- [c36]Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi: Active reversed nested Miller compensation for three-stage amplifiers. ISCAS 2006
- [c35]Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi: Analysis and evaluation of harmonic distortion in the tunnel diode oscillator. ISCAS 2006
- 2005
- [c34]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi: Well-defined design procedure for a three-stage CMOS OTA. ISCAS (3) 2005: 2579-2582
- [c33]Gaetano Palumbo, P. Tommasino, Alessandro Trifiletti: Optimized design of source coupled logic gates in GaAs HEMT technology. ISCAS (4) 2005: 3583-3586
- [c32]Massimo Alioto, Gaetano Palumbo: Design techniques for low-power cascaded CML gates. ISCAS (5) 2005: 4685-4688
- [c31]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. PATMOS 2005: 355-363
- 2004
- [j7]Massimo Alioto, Gaetano Palumbo, Massimo Poli: Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Trans. VLSI Syst. 12(10): 1094-1107 (2004)
- [c30]Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo: Low-voltage linear voltage regulator suitable for memories. ISCAS (1) 2004: 389-392
- [c29]Massimo Alioto, Gaetano Palumbo, Massimo Poli: A gate-level strategy to design Carry Select Adders. ISCAS (2) 2004: 465-468
- [c28]Gaetano Palumbo, Salvatore Pennisi: Harmonic distortion in three-stage nested-Miller-compensated amplifiers. ISCAS (1) 2004: 485-488
- [c27]
- 2003
- [j6]Massimo Alioto, Rosario Mita, Gaetano Palumbo: Performance evaluation of the low-voltage CML D-latch topology. Integration 36(4): 191-209 (2003)
- [c26]Gianluca Giustolisi, Gaetano Palumbo: A novel 1-V class-AB transconductor for improving speed performance in SC applications. ISCAS (1) 2003: 153-156
- [c25]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo: A 1-V CMOS output stage with high linearity. ISCAS (1) 2003: 225-228
- [c24]Gianluca Giustolisi, Gaetano Palumbo: A new method for evaluating harmonic distortion in push-pull output stages. ISCAS (1) 2003: 233-236
- [c23]
- [c22]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi: Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs. ISCAS (1) 2003: 525-528
- [c21]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo: Design of low-voltage low-power SC filters for high-frequency applications. ISCAS (1) 2003: 605-608
- 2002
- [j5]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi: Current-mode A/D fuzzy converter. IEEE T. Fuzzy Systems 10(4): 533-540 (2002)
- [j4]Massimo Alioto, Gaetano Palumbo: Analysis and comparison on full adder block in submicron technology. IEEE Trans. VLSI Syst. 10(6): 806-823 (2002)
- [c20]Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo, Agatino Pennisi, Gaetano Palumbo: Low Power Strategy for a TFT Controller. DSD 2002: 351-354
- [c19]Gaetano Palumbo, F. Pappalardo, S. Sannella: Evaluation on power reduction applying gated clock approaches. ISCAS (4) 2002: 85-88
- [c18]
- [c17]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo: Analysis and optimization of gain-boosted telescopic amplifiers. ISCAS (1) 2002: 321-324
- [c16]Gianluca Giustolisi, Gaetano Palumbo: Analysis of power supply noise attenuation in a PTAT current source. ISCAS (1) 2002: 561-564
- [c15]Massimo Alioto, Gaetano Palumbo, Massimo Poli: An Approach to Energy Consumption Modeling in RC Ladder Circuits. PATMOS 2002: 239-246
- [c14]Massimo Alioto, Gaetano Palumbo: Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. PATMOS 2002: 429-437
- [c13]Rosario Mita, Gaetano Palumbo: Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. PATMOS 2002: 468-476
- 2001
- [j3]Massimo Alioto, Gaetano Palumbo: Power estimation in adiabatic circuits: a simple and accurate model. IEEE Trans. VLSI Syst. 9(5): 608-615 (2001)
- [c12]Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton: Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. IOLTW 2001: 192-196
- [c11]Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115
- [c10]Rosario Mita, Gaetano Palumbo, Salvatore Pennisi: Reversed nested Miller compensation with current follower. ISCAS (1) 2001: 308-311
- [c9]Gaetano Palumbo, D. Pappalardo, M. Gaibotti: Modeling and minimization of power consumption in charge pump circuits. ISCAS (4) 2001: 402-405
- [c8]Gianluca Giustolisi, Gaetano Palumbo: Detailed frequency analysis of power supply rejection in Brokaw bandgap. ISCAS (1) 2001: 731-734
- 2000
- [c7]Massimo Alioto, Gaetano Palumbo: Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. PATMOS 2000: 265-275
1990 – 1999
- 1999
- [j2]Massimo Alioto, Gaetano Palumbo: Highly accurate and simple models for CML and ECL gates. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1369-1375 (1999)
- 1998
- [c6]Gianluca Giustolisi, Giovanni Palmisano, Gaetano Palumbo, C. Strano: A Novel 1.5-V Cmos Mixer. Great Lakes Symposium on VLSI 1998: 113-117
- [c5]Massimo Alioto, Gaetano Palumbo: Novel Simple Models Of Cml Propagation Delay. Great Lakes Symposium on VLSI 1998: 270-274
- 1995
- [j1]G. Calí, Giovanni Palmisano, Gaetano Palumbo, N. Aiello: An Area Efficient Current limiter for Automotive IC: Analysis and Design. Journal of Circuits, Systems, and Computers 5(3): 443-454 (1995)
- [c4]
- 1994
- [c3]Gaetano Palumbo: Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time. ISCAS 1994: 413-416
- [c2]Giuseppe Di Cataldo, Gaetano Palumbo: Optimized Design of 4 Stage Dickson Voltage Multiplier. ISCAS 1994: 693-696
- [c1]Giovanni Palmisano, Gaetano Palumbo, Salvatore Pennisi: A High-Accuracy High-Speed CMOS Current Comparator. ISCAS 1994: 739-742
Coauthor Index
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last updated on 2013-05-14 22:08 CEST by the dblp team