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Preeti Ranjan Panda
2010 – today
- 2013
[c46]Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda: Space sensitive cache dumping for post-silicon validation. DATE 2013: 497-502- [c45]Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan: Power Supply Efficiency Aware Server Allocation in Data Centers. VLSI Design 2013: 233-238
- 2012
- [j16]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda: Exploiting UML based validation for compliance checking of TLM 2 based models. Design Autom. for Emb. Sys. 16(2): 93-113 (2012)
- [c44]Prasenjit Chakraborty, Preeti Ranjan Panda: Integrating software caches with scratch pad memory. CASES 2012: 201-210
- [c43]Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi: Efficient on-line algorithm for maintaining k-cover of sparse bit-strings. FSTTCS 2012: 249-256
- 2011
- [j15]Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi: Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60(4): 484-497 (2011)
- [c42]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar: Exploiting temporal decoupling to accelerate trace-driven NoC emulation. CODES+ISSS 2011: 315-324
- [c41]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda: A SysML Profile for Development and Early Validation of TLM 2.0 Models. ECMFA 2011: 299-311
- [c40]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda: A UML based framework for efficient validation of TLM 2 models. FDL 2011: 1-8
- 2010
- [j14]Preeti Ranjan Panda, Rajendran Panda: Guest Editorial: Special Issue on VLSI Design and Embedded Systems. International Journal of Parallel Programming 38(3-4): 183-184 (2010)
- [c39]B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda: Rank based dynamic voltage and frequency scaling fortiled graphics processors. CODES+ISSS 2010: 3-12
- [c38]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar: FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. CODES+ISSS 2010: 247-256
- [c37]Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan: Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60
- [c36]Anshul Kumar, Preeti Ranjan Panda: Front-End Design Flows for Systems on Chip: An Embedded Tutorial. VLSI Design 2010: 417-422
2000 – 2009
- 2009
- [j13]Rajendran Panda, Preeti Ranjan Panda: A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. J. Low Power Electronics 5(3): 255-256 (2009)
- [c35]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Online cache state dumping for processor debug. DAC 2009: 358-363
- [c34]Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Cache aware compression for processor debug support. DATE 2009: 208-213
- [c33]Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda: A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE 2009: 1018-1023
- [c32]B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda: Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. ISVC (1) 2009: 111-124
- 2008
- [j12]Preeti Ranjan Panda: Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems. International Journal of Parallel Programming 36(1): 1-2 (2008)
- [c31]Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda: REWIRED - Register Write Inhibition by Resource Dedication. ASP-DAC 2008: 28-31
- [c30]B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran: Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD 2008: 559-564
- 2007
- [j11]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. International Journal of Parallel Programming 35(6): 507-527 (2007)
- [c29]Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda: The impact of loop unrolling on controller delay in high level synthesis. DATE 2007: 391-396
- [c28]Rahul Jain, Preeti Ranjan Panda: An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. ISCAS 2007: 1377-1380
- [c27]Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda: Power Reduction in VLIW Processor with Compiler Driven Bypass Network. VLSI Design 2007: 233-238
- [c26]Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda: Customization of Register File Banking Architecture for Low Power. VLSI Design 2007: 239-244
- [c25]Rahul Jain, Preeti Ranjan Panda: Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. VLSI Design 2007: 813-818
- 2006
- [c24]Preeti Ranjan Panda: Abridged addressing: a low power memory addressing strategy. ASP-DAC 2006: 892-897
- [c23]Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda: Rapid estimation of control delay from high-level specifications. DAC 2006: 455-458
- 2005
- [c22]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735
- [c21]Vikram Singh Saun, Preeti Ranjan Panda: Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. VLSI Design 2005: 280-285
- 2003
- [j10]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda: Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. VLSI Syst. 11(5): 928-938 (2003)
- [c20]Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran: Specification and Design of Multi-Million Gate SOCs. VLSI Design 2003: 18-19
- 2002
- [c19]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda: An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC 2002: 608-611
- [c18]Preeti Ranjan Panda, Nikil D. Dutt: Memory Architectures for Embedded Systems-On-Chip. HiPC 2002: 647-662
- [c17]Preeti Ranjan Panda, Lakshmikantam Chitturi: An energy-conscious algorithm for memory port allocation. ICCAD 2002: 572-576
- 2001
- [j9]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef: Data Memory Organization and Optimizations in Application-Specific Systems. IEEE Design & Test of Computers 18(3): 56-68 (2001)
- [j8]Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg: Data and memory optimization techniques for embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 149-206 (2001)
- [c16]
- [c15]Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda: New design paradigms. ISSS 2001: 94
- [c14]Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli: Cache-efficient memory layout of aggregate data structures. ISSS 2001: 101-106
- [c13]Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda: Embedded Memories in System Design: Technology, Application, Design and Tools. VLSI Design 2001: 5-6
- 2000
- [j7]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electr. Syst. 5(3): 682-704 (2000)
1990 – 1999
- 1999
- [j6]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999)
- [j5]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Local memory exploration and optimization in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 3-13 (1999)
- [j4]Preeti Ranjan Panda, Nikil D. Dutt: Low-power memory mapping through reducing address bus activity. IEEE Trans. VLSI Syst. 7(3): 309-320 (1999)
- [c12]Preeti Ranjan Panda: Memory bank customization and assignment in behavioral synthesis. ICCAD 1999: 477-481
- 1998
- [j3]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Incorporating DRAM access modes into high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 96-109 (1998)
- [c11]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Data Cache Sizing for Embedded Processor Applications. DATE 1998: 925-926
- 1997
- [j2]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory data organization for improved cache performance in embedded processor applications. ACM Trans. Design Autom. Electr. Syst. 2(4): 384-409 (1997)
- [c10]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997: 7-11
- [c9]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Exploiting off-chip memory access modes in high-level synthesis. ICCAD 1997: 333-340
- [c8]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: A Data Alignment Technique for Improving Cache Performance. ICCD 1997: 587-592
- [c7]Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Improving cache Performance Through Tiling and Data Alignment. IRREGULAR 1997: 167-185
- [c6]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Architectural Exploration and Optimization of Local Memory in Embedded Systems. ISSS 1997: 90-
- [c5]Preeti Ranjan Panda, Nikil D. Dutt: Behavioral Array Mapping into Multiport Memories Targeting Low Power. VLSI Design 1997: 268-273
- 1996
- [c4]Preeti Ranjan Panda, Nikil D. Dutt: Low-power mapping of behavioral arrays to multiple memories. ISLPED 1996: 289-292
- [c3]Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory Organization for Improved Data Cache Performance in Embedded Processors. ISSS 1996: 90-95
- 1995
- [c2]
- 1993
- [j1]Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri: Estimating the Complexity of Synthesized Designs from FSM Specifications. IEEE Design & Test of Computers 10(1): 30-35 (1993)
- 1991
- [c1]Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri: A Flexible Scheme for State Assignment Based on Characteristics of the FSM. ICCAD 1991: 226-229
Coauthor Index
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last updated on 2013-05-19 19:31 CEST by the dblp team