| 2012 | ||
|---|---|---|
| c10 | Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael J. Schulte, William Lloyd Bircher, Madhu S. Sibi Govindan: AUDIT: Stress Testing the Automatic Way. MICRO 2012: 212-223 | |
| 2009 | ||
| j2 | Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David Blaauw: Energy-Efficient Subthreshold Processor Design. IEEE Trans. VLSI Syst. 17(8): 1127-1137 (2009) | |
| 2007 | ||
| j1 | Sanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007) | |
| c9 | Sanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762 | |
| 2006 | ||
| c8 | ||
| c7 | Sanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006 | |
| 2005 | ||
| c6 | Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371 | |
| c5 | Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207 | |
| 2004 | ||
| c4 | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176 | |
| c3 | Woo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136 | |
| 2003 | ||
| c2 | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192 | |
| c1 | Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18 | |
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