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 | 2013 | |
|---|---|---|
| j20 |      | Osama Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel, Christos A. Papachristou: High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic. Microprocessors and Microsystems - Embedded Hardware Design 37(3): 287-298 (2013) |
| 2012 | ||
| c100 | | Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou: A low power memory cell design for SEU protection against radiation effects. AHS 2012: 288-295 |
| c99 | | Lawrence Leinweber, Christos A. Papachristou, Francis G. Wolff: An efficient elliptic curve cryptography processor using addition chains with high information entropy. CCECE 2012: 1-6 |
| 2011 | ||
| j19 | | Huthaifa Al-Omari, Christos A. Papachristou, Francis G. Wolff, David R. McIntyre: Smoothing delay jitter in networked control systems. J. Embedded Computing 4(1): 11-21 (2011) |
| c98 | | Lawrence Leinweber, Christos A. Papachristou, Francis G. Wolff: An analysis of efficient formulas for elliptic curve point addition over binary extension fields. CISS 2011: 1-5 |
| c97 | | Osama Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel, Christos A. Papachristou, Francis G. Wolff: Fast and compact binary-to-BCD conversion circuits for decimal multiplication. ICCD 2011: 226-231 |
| c96 | | Osama Al-Khaleel, Mohammad Al-Khaleel, Zakaria Al-Qudah, Christos A. Papachristou, Khaldoon Mhaidat, Francis G. Wolff: Fast binary/decimal adder/subtractor with a novel correction-free BCD addition. ICECS 2011: 455-459 |
| c95 | | Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou: A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS. IOLTS 2011: 139-144 |
| c94 | | Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou: Noise margin, critical charge and power-delay tradeoffs for SRAM design. IOLTS 2011: 145-150 |
| 2010 | ||
| c93 | | Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Swarup Bhunia: System level self-healing for parametric yield and reliability improvement under power bound. AHS 2010: 52-58 |
| c92 | | Yuriy Shiyanovskii, Francis G. Wolff, Aravind Rajendran, Christos A. Papachristou, Daniel J. Weyer, W. Clay: Process reliability based trojans through NBTI and HCI effects. AHS 2010: 215-222 |
| c91 | | Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, W. Clay: Embedded system protection from software corruption. AHS 2010: 223-229 |
| c90 | | Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia: Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18 |
| c89 | | David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia: Trustworthy computing in a multi-core system using distributed scheduling. IOLTS 2010: 211-213 |
| 2009 | ||
| c88 | | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer: An Adaptable Task Manager for Reconfigurable Architecture Kernels. AHS 2009: 132-137 |
| c87 | | Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia: MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410 |
| c86 | | Huthaifa Al-Omari, Francis G. Wolff, Christos A. Papachristou, David R. McIntyre: Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model. CSE (2) 2009: 295-302 |
| c85 | | David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia: Dynamic Evaluation of Hardware Trust. HOST 2009: 108-111 |
| c84 | | Lawrence Leinweber, Christos A. Papachristou, Francis G. Wolff: Efficient architectures for elliptic curve cryptography processors for RFID. ICCD 2009: 372-377 |
| c83 | | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou: SRAM cell design using tri-state devices for SEU protection. IOLTS 2009: 114-119 |
| c82 | | Huthaifa Al-Omari, Francis G. Wolff, Christos A. Papachristou, David R. McIntyre: An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems. ScalCom-EmbeddedCom 2009: 81-86 |
| i2 | | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, W. Clay: Hardware Trojan by Hot Carrier Injection. CoRR abs/0906.3832 (2009) |
| i1 | | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, W. Clay: Exploiting Semiconductor Properties for Hardware Trojans. CoRR abs/0906.3834 (2009) |
| 2008 | ||
| c81 | | Gorn Tepvorachai, Christos A. Papachristou: Face Recognition using a Cognitive Processing Model. AHS 2008: 505-512 |
| c80 | | Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty: Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. DATE 2008: 1362-1365 |
| c79 | | Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou: A high-speed radix-4 multiplexer-based array multiplier. ACM Great Lakes Symposium on VLSI 2008: 115-118 |
| c78 | | Francis G. Wolff, Christos A. Papachristou: An Embedded Flash Memory Vault for Software Trojan Protection. HOST 2008: 97-99 |
| c77 | | Gorn Tepvorachai, Christos A. Papachristou: Multi-label imbalanced data enrichment process in neural net classifier training. IJCNN 2008: 1301-1307 |
| c76 | | Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou: SRAM Cell Design Protected from SEU Upsets. IOLTS 2008: 169-170 |
| 2007 | ||
| c75 | | Gorn Tepvorachai, Christos A. Papachristou: A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure. AHS 2007: 176-183 |
| c74 | | Gorn Tepvorachai, Christos A. Papachristou: Facial Image Associative Memory Model. AHS 2007: 233-242 |
| c73 | | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff: Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. DATE 2007: 1460-1465 |
| c72 | | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. IOLTS 2007: 71-78 |
| 2006 | ||
| j18 | | Hani Rizk, Christos A. Papachristou, Francis G. Wolff: A Self Test Program Design Technique for Embedded DSP Cores. J. Electronic Testing 22(1): 71-87 (2006) |
| j17 | | Shih-yu Yang, Christos A. Papachristou: A method for detecting interconnect DSM defects in systems on chip. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 197-204 (2006) |
| c71 | | Gorn Tepvorachai, Christos A. Papachristou: Self-Configurable Neural Network Processor for FIR Filter Applications. AHS 2006: 114-121 |
| c70 | | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: A Large Scale Adaptable Multiplier for Cryptographic Applications. AHS 2006: 477-484 |
| c69 | | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff: Soft delay error analysis in logic circuits. DATE 2006: 47-52 |
| c68 | | Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff: A Dynamic Reconfigurable Fabric for Platform SoCs. FPL 2006: 1-4 |
| c67 | | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. ICCD 2006 |
| 2005 | ||
| c66 | | Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick: An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. DATE 2005: 592-597 |
| c65 | | Jianchun Li, Christos A. Papachristou, Raj Shekhar: Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only). FPGA 2005: 279 |
| c64 | | Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou: Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. IOLTS 2005: 266-271 |
| c63 | | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff, Norbert Seifert: Node sensitivity analysis for soft errors in CMOS logic. ITC 2005: 9 |
| 2004 | ||
| c62 | | Francis G. Wolff, Christos A. Papachristou, David R. McIntyre: Test Compression and Hardware Decompression for Scan-Based SoCs. DATE 2004: 716-717 |
| c61 | | Hani Rizk, Christos A. Papachristou, Francis G. Wolff: Designing Self Test Programs for Embedded DSP Cores. DATE 2004: 816-823 |
| c60 | | Jianchun Li, Christos A. Papachristou, Raj Shekhar: A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing. FCCM 2004: 320-321 |
| c59 |  | Jianchun Li, Christos A. Papachristou, Raj Shekhar: A "Brick" Caching Scheme for 3D Medical Imaging. ISBI 2004: 563-566 |
| c58 | | Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff: Soft Delay Error Effects in CMOS Combinational Circuits. VTS 2004: 325-334 |
| 2003 | ||
| c57 | | Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre: A Technique for High Ratio LZW Compression. DATE 2003: 10116-10121 |
| 2002 | ||
| j16 | | Mehrdad Nourani, Christos A. Papachristou: False path exclusion in delay analysis of RTL structures. IEEE Trans. VLSI Syst. 10(1): 30-43 (2002) |
| c56 | | Francis G. Wolff, Christos A. Papachristou: Multiscan-Based Test Compression and Hardware Decompression Using LZ77. ITC 2002: 331-339 |
| 2001 | ||
| j15 | | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Integrated test of interacting controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001) |
| c55 | | Kelly A. Ockunzzi, Christos A. Papachristou: Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. DAC 2001: 65-70 |
| c54 | | Shih-yu Yang, Christos A. Papachristou, Massood Tabib-Azar: Improving Bus Test Via IDDT and Boundary Scan. DAC 2001: 307-312 |
| c53 | | Kelly A. Ockunzzi, Christos A. Papachristou: Breaking Correlation to Improve Testability. VTS 2001: 75-81 |
| 2000 | ||
| j14 | | Mehrdad Nourani, Christos A. Papachristou: Stability-based algorithms for high-level synthesis of digital ASICs. IEEE Trans. VLSI Syst. 8(4): 431-435 (2000) |
| c52 | | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Synthesis-for-testability of controller-datapath pairs that use gated clocks. DAC 2000: 613-618 |
| c51 | | Joan Carletta, Christos A. Papachristou, Mehrdad Nourani: Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728 |
| c50 | | Mehrdad Nourani, Christos A. Papachristou: An ILP formulation to optimize test access mechanism in system-on-chip testing. ITC 2000: 902-910 |
| 1999 | ||
| j13 | | Mehrdad Nourani, Christos A. Papachristou: Structural Fault Testing of Embedded Cores Using Pipelining. J. Electronic Testing 15(1-2): 129-144 (1999) |
| j12 | | Christos A. Papachristou, Mehrdad Nourani, Mark Spining: A multiple clocking scheme for low-power RTL design. IEEE Trans. VLSI Syst. 7(2): 266-276 (1999) |
| c49 | | Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou: Using codesign techniques to support analog functionality. CODES 1999: 79-84 |
| c48 | | Christos A. Papachristou, F. Martin, Mehrdad Nourani: Microprocessor Based Testing for Core-Based System on Chip. DAC 1999: 586-591 |
| c47 | | Joan Carletta, Mehrdad Nourani, Christos A. Papachristou: Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. DATE 1999: 278-282 |
| c46 | | Christos A. Papachristou, Yusuf Alzazeri: A Method of Distributed Controller Design for RTL Circuits. DATE 1999: 774-775 |
| c45 | | |
| c44 | | Ken Batcher, Christos A. Papachristou: Instruction Randomization Self Test For Processor Cores. VTS 1999: 34-40 |
| 1998 | ||
| j11 | | Christos A. Papachristou, Mikhail Baklashov, Kowen Lai: High-Level Test Synthesis for Behavioral and Structural Designs. J. Electronic Testing 13(2): 167-188 (1998) |
| j10 | | Kelly A. Ockunzzi, Christos A. Papachristou: Testability Enhancement for Control-Flow Intensive Behaviors. J. Electronic Testing 13(3): 239-257 (1998) |
| c43 | | |
| c42 | | Mehrdad Nourani, Christos A. Papachristou: A Bypass Scheme for Core-Based System Fault Testing. DATE 1998: 979-980 |
| c41 | | Mehrdad Nourani, Christos A. Papachristou: Parallelism in Structural Fault Testing of Embedded Cores. VTS 1998: 15-21 |
| 1997 | ||
| j9 | | Joan Carletta, Christos A. Papachristou: Behavioral Testability Insertion for Datapath/Controller Circuits. J. Electronic Testing 11(1): 9-28 (1997) |
| c40 | | Kowen Lai, Christos A. Papachristou, Mikhail Baklashov: BIST testability enhancement using high level test synthesis for behavioral and structural designs. Asian Test Symposium 1997: 338-342 |
| c39 | | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: A Scheme for Integrated Controller-Datapath Fault Testing. DAC 1997: 546-551 |
| c38 | | Mehrdad Nourani, Christos A. Papachristou: Structural BIST insertion using behavioral test analysis. ED&TC 1997: 64-68 |
| c37 | | Christos A. Papachristou, Mikhail Baklashov: A test synthesis technique using redundant register transfers. ICCAD 1997: 414-420 |
| c36 | | Kowen Lai, Christos A. Papachristou, Mikhail Baklashov: High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains. ICCD 1997: 636-641 |
| c35 | | Kelly A. Ockunzzi, Christos A. Papachristou: Testability Enhancement for Behavioral Descriptions Containing Conditional Statements. ITC 1997: 236-245 |
| 1996 | ||
| c34 | | Kowen Lai, Christos A. Papachristou: BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. Asian Test Symposium 1996: 219- |
| c33 | | Ehat Ercanli, Christos A. Papachristou: A Register File and Scheduling Model for Application Specific Processor Synthesis. DAC 1996: 35-40 |
| c32 | | Christos A. Papachristou, Mark Spining, Mehrdad Nourani: An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. DAC 1996: 337-342 |
| c31 | | Wei Zhao, Christos A. Papachristou: Synthesis of reusable DSP cores based on multiple behaviors. ICCAD 1996: 103-108 |
| c30 | | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard: Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507 |
| 1995 | ||
| j8 | | Wen-Ben Jone, Christos A. Papachristou: A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 374-384 (1995) |
| c29 | | Wei Zhao, Christos A. Papachristou: Architectural partitioning of control memory for application specific programmable processors. ICCAD 1995: 521-526 |
| c28 | | Joan Carletta, Christos A. Papachristou: Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ICCD 1995: 162-167 |
| c27 | | Christos A. Papachristou, Mark Spining, Mehrdad Nourani: A multiple clocking scheme for low power RTL design. ISLPD 1995: 27-32 |
| c26 | | |
| c25 | | Joan Carletta, Christos A. Papachristou: Structural constraints for circular self-test paths. VTS 1995: 486-491 |
| 1994 | ||
| c24 | | Joan Carletta, Christos A. Papachristou: Structural constraints for circular self-test paths. VTS 1994: 87-92 |
| 1993 | ||
| j7 | | Christos A. Papachristou, Venkata R. Immaneni: Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing. IEEE Trans. Computers 42(1): 45-61 (1993) |
| c23 | | Mehrdad Nourani, Christos A. Papachristou: A Layout Estimation Algorithm for RTL Datapaths. DAC 1993: 285-291 |
| c22 | | Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani: An Approach for Redesigning in Data Path Synthesis. DAC 1993: 419-423 |
| c21 | | Haidar Harmanani, Christos A. Papachristou: An improved method for RTL synthesis with testability tradeoffs. ICCAD 1993: 30-35 |
| c20 | | Scott Chiu, Christos A. Papachristou: A Partial Scan Cost Estimation Method at the System Level. ICCD 1993: 146-150 |
| c19 | | H. Fatih Ugurdag, Christos A. Papachristou: A VLIW architecture based on shifting register files. MICRO 1993: 263-268 |
| 1992 | ||
| c18 | | Mehrdad Nourani, Christos A. Papachristou: Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. DAC 1992: 99-105 |
| c17 | | H. Fatih Ugurdag, Christos A. Papachristou: ALMP: A Shifting Memory Architecture for Loop Pipelining. ICCD 1992: 564-568 |
| c16 | | Michael J. Knieser, Christos A. Papachristou: Y-Pipe: a conditional branching scheme without pipeline delays. MICRO 1992: 125-128 |
| 1991 | ||
| c15 | | Scott Chiu, Christos A. Papachristou: A Design for Testability Scheme with Applications to Data Path Synthesis. DAC 1991: 271-277 |
| c14 | | Christos A. Papachristou, Scott Chiu, Haidar Harmanani: A Data Path Synthesis Method for Self-Testable Designs. DAC 1991: 378-384 |
| c13 | | Scott Chiu, Christos A. Papachristou: A Built-In Self-Testing Approach for Minimizing Hardware Overhead. ICCD 1991: 282-285 |
| c12 | | Christos A. Papachristou, Scott Chiu, Haidar Harmanani: SYNTEST: A Method for High-Level SYNthesis with Self-TESTability. ICCD 1991: 458-462 |
| 1990 | ||
| j6 | | Christos A. Papachristou, Anil L. Pandya: A design scheme for PLA-based control tables with reduced area and time-delay cost. IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 453-472 (1990) |
| c11 | | Christos A. Papachristou, Haluk Konuk: A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. DAC 1990: 77-83 |
| c10 | | Jong-Jiann Shieh, Christos A. Papachristou: An instruction reoderer for pipelined computers. MICRO 1990: 135-142 |
| c9 | | Djahida Smati, Jerry Hwang, Christos A. Papachristou: SMDSS - a structured microcode development and simulation system. MICRO 1990: 252-259 |
| 1989 | ||
| c8 | | Wen-Ben Jone, Christos A. Papachristou: A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. DAC 1989: 525-534 |
| c7 | | Wen-Ben Jone, Christos A. Papachristou, M. Pereira: A Scheme for Overlaying Concurrent Testing of VLSI Circuits. DAC 1989: 531-536 |
| c6 | | Jong-Jiann Shieh, Christos A. Papachristou: On reordering instruction streams for pipelined computers. MICRO 1989: 199-206 |
| 1988 | ||
| c5 | | L. Shih, Christos A. Papachristou: Mapping of micro data flow computations on parallel microarchitectures. MICRO 1988: 70-72 |
| 1987 | ||
| j5 | | Christos A. Papachristou: Associative table lookup processing for multioperand residue arithmetic. J. ACM 34(2): 376-396 (1987) |
| c4 | | Christos A. Papachristou, Suntae Hwang: A Systolic Array Structure for Matrix Multiplication in the Residue Number System. ICS 1987: 716-731 |
| 1986 | ||
| c3 | | Christos A. Papachristou: Expert system approach to VLSI cell design (abstract). ACM Conference on Computer Science 1986: 485 |
| 1985 | ||
| j4 | | Christos A. Papachristou, Narendar B. Sahgal: An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories. IEEE Trans. Computers 34(2): 110-116 (1985) |
| c2 | | Christos A. Papachristou: Multi - Input residue arithmetic utilizing read - Only associative memory. IEEE Symposium on Computer Arithmetic 1985: 182-188 |
| 1983 | ||
| j3 | | Christos A. Papachristou: Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach. IEEE Trans. Computers 32(10): 961-968 (1983) |
| 1981 | ||
| c1 | | Christos A. Papachristou: Algorithms for parallel addition and parallel polynomial evaluation. IEEE Symposium on Computer Arithmetic 1981: 256-263 |
| 1978 | ||
| j2 | | Christos A. Papachristou: An Algorithm for Optimal NAND Cascade Logic Synthesis. IEEE Trans. Computers 27(12): 1099-1111 (1978) |
| 1977 | ||
| j1 | | Christos A. Papachristou: Characteristic measures of switching functions. Inf. Sci. 13(1): 51-75 (1977) |
Colors in the list of coauthors
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