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 | 2013 | |
|---|---|---|
| c17 |      | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne: Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 |
| 2012 | ||
| c16 | | Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne: Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA 2012: 119-128 |
| c15 | | Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk: Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 |
| 2011 | ||
| j5 | | Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne: Compressor tree synthesis on commercial high-performance FPGAs. TRETS 4(4): 39 (2011) |
| c14 | | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne: Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 |
| c13 | | Hadi Parandeh-Afshar, Paolo Ienne: Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL 2011: 225-231 |
| 2010 | ||
| j4 | | Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne: Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. VLSI Syst. 18(4): 578-590 (2010) |
| c12 | | Hadi Parandeh-Afshar, Paolo Ienne: Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM 2010: 229-236 |
| c11 | | Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24 |
| 2009 | ||
| j3 | | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2) (2009) |
| j2 | | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. TRETS 2(3) (2009) |
| c10 | | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286 |
| c9 | | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249 |
| c8 | | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 |
| c7 | | Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 |
| 2008 | ||
| c6 | | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 |
| c5 | | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 |
| c4 | | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 |
| c3 | | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 |
| 2007 | ||
| j1 | | Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram: Fast INC-XOR codec for low-power address buses. IET Computers & Digital Techniques 1(5): 625-626 (2007) |
| c2 | | Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 |
| 2006 | ||
| c1 | | Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz: A very high performance address BUS encoder. ISCAS 2006 |
Colors in the list of coauthors
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