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 | 2013 | |
|---|---|---|
| j108 |      | Te-Lung Kung, Keshab K. Parhi: Semiblind frequency-domain timing synchronization and channel estimation for OFDM systems. EURASIP J. Adv. Sig. Proc. 2013: 1 (2013) |
| j107 | | Te-Lung Kung, Keshab K. Parhi: Performance evaluation of variable transmission rate OFDM systems via network source coding. EURASIP J. Adv. Sig. Proc. 2013: 12 (2013) |
| j106 | | Chuan Zhang, Keshab K. Parhi: Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder. IEEE Transactions on Signal Processing 61(10): 2429-2441 (2013) |
| j105 | | Keshab K. Parhi: Comments on "Low-energy CSMT carry generators and binary adders". IEEE Trans. VLSI Syst. 21(4): 791 (2013) |
| j104 | | Yingbo Hu, Keshab K. Parhi: Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits. Signal Processing Systems 70(3): 259-274 (2013) |
| 2012 | ||
| j103 | | Aaron E. Cohen, Jian-Hung Lin, Keshab K. Parhi: Variable data rate (VDR) network congestion control (NCC) applied to voice/audio communication. Computer Networks 56(4): 1343-1356 (2012) |
| j102 | | Hua Jiang, Marc D. Riedel, Keshab K. Parhi: Digital Signal Processing With Molecular Reactions. IEEE Design & Test of Computers 29(3): 21-31 (2012) |
| j101 | | Chuan Zhang, Keshab K. Parhi: A Network-Efficient Nonbinary QC-LDPC Decoder Architecture. IEEE Trans. on Circuits and Systems 59-I(6): 1359-1371 (2012) |
| j100 | | Manohar Ayinala, Michael Brown, Keshab K. Parhi: Pipelined Parallel FFT Architectures via Folding Transformation. IEEE Trans. VLSI Syst. 20(6): 1068-1081 (2012) |
| c110 | | Manohar Ayinala, Keshab K. Parhi: Parallel pipelined FFT architectures with reduced number of delays. ACM Great Lakes Symposium on VLSI 2012: 63-66 |
| c109 | | Sayed Ahmad Salehi, Rasoul Amirfattahi, Keshab K. Parhi: Efficient folded VLSI architectures for linear prediction error filters. ACM Great Lakes Symposium on VLSI 2012: 357-362 |
| c108 | | Chuan Zhang, Bo Yuan, Keshab K. Parhi: Reduced-latency SC polar decoder architectures. ICC 2012: 3471-3475 |
| 2011 | ||
| j99 | | Renfei Liu, Keshab K. Parhi: Power Reduction in Frequency-Selective FIR Filters Under Voltage Overscaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 343-356 (2011) |
| j98 | | Aaron E. Cohen, Keshab K. Parhi: Secure Variable Data Rate Transmission. IEEE Trans. on Circuits and Systems 58-II(2): 100-104 (2011) |
| j97 | | Manohar Ayinala, Keshab K. Parhi: High-Speed Parallel Architectures for Linear Feedback Shift Registers. IEEE Transactions on Signal Processing 59(9): 4459-4469 (2011) |
| c107 | | Hua Jiang, Marc D. Riedel, Keshab K. Parhi: Synchronous sequential computation with molecular reactions. DAC 2011: 836-841 |
| c106 | | Hemant A. Patil, Maulik C. Madhavi, Keshab K. Parhi: Combining Evidence from Spectral and Source-Like Features for Person Recognition from Humming. INTERSPEECH 2011: 369-372 |
| i3 | | Chuan Zhang, Keshab K. Parhi: Efficient Network for Non-Binary QC-LDPC Decoder. CoRR abs/1111.0703 (2011) |
| i2 | | Chuan Zhang, Bo Yuan, Keshab K. Parhi: Reduced-Latency SC Polar Decoder Architectures. CoRR abs/1111.0704 (2011) |
| i1 | | Chuan Zhang, Bo Yuan, Keshab K. Parhi: Low-Latency SC Decoder Architectures for Polar Codes. CoRR abs/1111.0705 (2011) |
| 2010 | ||
| j96 | | Daesun Oh, Keshab K. Parhi: Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes. IEEE Trans. on Circuits and Systems 57-I(1): 105-115 (2010) |
| j95 | | Daesun Oh, Keshab K. Parhi: Low-Complexity Switch Network for Reconfigurable LDPC Decoders. IEEE Trans. VLSI Syst. 18(1): 85-94 (2010) |
| j94 | | Yang Liu, Tong Zhang, Keshab K. Parhi: Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage. IEEE Trans. VLSI Syst. 18(4): 517-526 (2010) |
| j93 | | Aaron E. Cohen, Keshab K. Parhi: Fast Reconfigurable Elliptic Curve Cryptography Acceleration for GF(2m) on 32 bit Processors. Signal Processing Systems 60(1): 31-45 (2010) |
| c105 | | Xiaoming Zhu, Keshab K. Parhi: Underdetermined blind source separation based on Continuous Density Hidden Markov Models. ICASSP 2010: 4126-4129 |
| c104 | | Hemant A. Patil, Keshab K. Parhi: Novel Variable length Teager Energy Based features for person recognition from their hum. ICASSP 2010: 4526-4529 |
| c103 | | Yun Park, Theoden I. Netoff, Keshab K. Parhi: Seizure prediction with spectral power of time/space-differential EEG signals using cost-sensitive support vector machine. ICASSP 2010: 5450-5453 |
| c102 | | Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, Keshab K. Parhi: A synthesis flow for digital signal processing with biomolecular reactions. ICCAD 2010: 417-424 |
| c101 | | Adam Shea, Brian Fett, Marc D. Riedel, Keshab K. Parhi: Writing and Compiling Code into Biochemistry. Pacific Symposium on Biocomputing 2010: 456-464 |
| 2009 | ||
| j92 | | Chester Sungchung Park, Keshab K. Parhi, Sin-Chong Park: Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems. IEEE Trans. on Circuits and Systems 56-I(3): 685-698 (2009) |
| j91 | | Jie Chen, Yongru Gu, Keshab K. Parhi: Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission. IEEE Trans. on Circuits and Systems 56-I(6): 1272-1285 (2009) |
| j90 | | Renfei Liu, Keshab K. Parhi: Low-Latency Low-Complexity Architectures for Viterbi Decoders. IEEE Trans. on Circuits and Systems 56-I(10): 2315-2324 (2009) |
| j89 | | Mario Garrido, Keshab K. Parhi, Jesús Grajal: A Pipelined FFT Architecture for Real-Valued Signals. IEEE Trans. on Circuits and Systems 56-I(12): 2634-2643 (2009) |
| j88 | | Aaron E. Cohen, Keshab K. Parhi: A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet. IEEE Transactions on Signal Processing 57(10): 4085-4094 (2009) |
| j87 | | Ebrahim Saberinia, Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi: Pulsed-OFDM Modulation for Ultrawideband Communications. IEEE T. Vehicular Technology 58(2): 720-726 (2009) |
| j86 | | Daesun Oh, Keshab K. Parhi: Low Complexity Decoder Architecture for Low-Density Parity-Check Codes. Signal Processing Systems 56(2-3): 217-228 (2009) |
| c100 | | Adam Shea, Marc D. Riedel, Brian Fett, Keshab K. Parhi: Synthesizing sequential register-based computation with biochemistry. ICCAD 2009: 136-143 |
| c99 | | |
| c98 | | Renfei Liu, Keshab K. Parhi: Noise Reduction for Low-power Broadband Filtering. ISCAS 2009: 1012-1015 |
| c97 | | Hemant A. Patil, Keshab K. Parhi: Variable Length Teager Energy Based Mel Cepstral Features for Identification of Twins. PReMI 2009: 525-530 |
| c96 | | Renfei Liu, Keshab K. Parhi: Sparse severe error removal in OFDM demodulators for erasure channels. SiPS 2009: 001-006 |
| 2008 | ||
| j85 | | Yongru Gu, Keshab K. Parhi: Design of Parallel Tomlinson-Harashima Precoders. IEEE Trans. on Circuits and Systems 55-II(5): 447-451 (2008) |
| j84 | | Jie Chen, Yongru Gu, Keshab K. Parhi: Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers. IEEE Trans. on Circuits and Systems 55-I(9): 2827-2840 (2008) |
| j83 | | Chao Cheng, Keshab K. Parhi: Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders. IEEE Trans. on Circuits and Systems 55-II(12): 1254-1258 (2008) |
| j82 | | Chao Cheng, Keshab K. Parhi: High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform. IEEE Transactions on Signal Processing 56(1): 393-403 (2008) |
| c95 | | Renfei Liu, Keshab K. Parhi: Fast composite field S-box architectures for advanced encryption standard. ACM Great Lakes Symposium on VLSI 2008: 65-70 |
| c94 | | Daesun Oh, Keshab K. Parhi: Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes. ACM Great Lakes Symposium on VLSI 2008: 451-456 |
| c93 | | Daesun Oh, Keshab K. Parhi: Area efficient controller design of barrel shifters for reconfigurable LDPC decoders. ISCAS 2008: 240-243 |
| c92 | | Renfei Liu, Keshab K. Parhi: Minimal complexity low-latency architectures for Viterbi decoders. SiPS 2008: 140-145 |
| c91 | | |
| 2007 | ||
| j81 | | Yongru Gu, Keshab K. Parhi: Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper. IEEE Transactions on Signal Processing 55(2): 707-715 (2007) |
| c90 | | Daesun Oh, Keshab K. Parhi: Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. ISCAS 2007: 1855-1858 |
| c89 | | |
| c88 | | Daesun Oh, Keshab K. Parhi: Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes. ISCAS 2007: 2758-2761 |
| 2006 | ||
| j80 | | Chao Cheng, Keshab K. Parhi: Hardware Efficient Fast Computation of the Discrete Fourier Transform. VLSI Signal Processing 42(2): 159-171 (2006) |
| j79 | | Yongru Gu, Keshab K. Parhi: Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper. VLSI Signal Processing 42(3): 211-221 (2006) |
| j78 | | Chao Cheng, Keshab K. Parhi: Hardware efficient fast computation of the discrete fourier transform. VLSI Signal Processing 43(1): 105-106 (2006) |
| j77 | | Lijun Gao, Keshab K. Parhi: Models for Architectural Power and Power Grid Noise Analysis on Data Bus. VLSI Signal Processing 44(1-2): 25-46 (2006) |
| c87 | | |
| c86 | | Aaron E. Cohen, Keshab K. Parhi: Faster elliptic curve point multiplication based on a novel greedy base-2, 3 method. ISCAS 2006 |
| c85 | | |
| c84 | | Yuping Zhang, Jun Tang, Keshab K. Parhi: Low Complexity List Updating Circuits for List Sphere Decoders. SiPS 2006: 28-33 |
| c83 | | Jian-Hung Lin, Keshab K. Parhi: Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system. SiPS 2006: 45-50 |
| c82 | | |
| c81 | | |
| 2005 | ||
| j76 | | Xinmiao Zhang, Keshab K. Parhi: Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Trans. VLSI Syst. 13(4): 413-426 (2005) |
| j75 | | Keshab K. Parhi: Design of multigigabit multiplexer-loop-based decision feedback equalizers. IEEE Trans. VLSI Syst. 13(4): 489-493 (2005) |
| j74 | | Xinmiao Zhang, Keshab K. Parhi: High-Speed Architectures for Parallel Long BCH Encoders. IEEE Trans. VLSI Syst. 13(7): 872-877 (2005) |
| j73 | | |
| j72 | | Yanni Chen, Keshab K. Parhi: On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes. VLSI Signal Processing 39(1-2): 35-47 (2005) |
| c80 | | Sang-Min Kim, Jun Tang, Keshab K. Parhi: Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems. ISCAS (1) 2005: 65-68 |
| c79 | | |
| c78 | | Chao Cheng, Keshab K. Parhi: Further complexity reduction of parallel FIR filters. ISCAS (2) 2005: 1835-1838 |
| c77 | | Jian-Hung Lin, Keshab K. Parhi: VLSI architectures for stereoscopic video disparity matching and object extraction. ISCAS (3) 2005: 2373-2376 |
| 2004 | ||
| j71 | | Zhipei Chi, Leilei Song, Keshab K. Parhi: On The Performance/Complexity Tradeoff in Block Turbo Decoder Design. IEEE Transactions on Communications 52(2): 173-175 (2004) |
| j70 | | Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi: On the better protection of short-frame turbo codes. IEEE Transactions on Communications 52(9): 1435-1439 (2004) |
| j69 | | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004) |
| j68 | | Tong Zhang, Keshab K. Parhi: Joint (3, k)-regular LDPC code and decoder/encoder design. IEEE Transactions on Signal Processing 52(4): 1065-1079 (2004) |
| j67 | | Jun Ma, Keshab K. Parhi: Pipelined CORDIC-based state-space orthogonal recursive digital filters using matrix look-ahead. IEEE Transactions on Signal Processing 52(7): 2102-2119 (2004) |
| j66 |  | Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi: Design of low-error fixed-width modified booth multiplier. IEEE Trans. VLSI Syst. 12(5): 522-531 (2004) |
| j65 | | Yanni Chen, Keshab K. Parhi: Small area parallel Chien search architectures for long BCH codes. IEEE Trans. VLSI Syst. 12(5): 545-549 (2004) |
| j64 | | Jun Jin Kong, Keshab K. Parhi: Low-latency architectures for high-throughput rate Viterbi decoders. IEEE Trans. VLSI Syst. 12(6): 642-651 (2004) |
| j63 | | Xinmiao Zhang, Keshab K. Parhi: High-speed VLSI architectures for the AES algorithm. IEEE Trans. VLSI Syst. 12(9): 957-967 (2004) |
| c76 | | Xinmiao Zhang, Keshab K. Parhi: High-speed architectures for parallel long BCH encoders. ACM Great Lakes Symposium on VLSI 2004: 1-6 |
| c75 | | Ebrahim Saberinia, Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi: Design and implementation of multi-band pulsed-OFDM system for wireless personal area networks. ICC 2004: 862-866 |
| c74 | | Keshab K. Parhi: Eliminating the fanout bottleneck in parallel long BCH encoders. ICC 2004: 2611-2615 |
| c73 | | Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi: Reduced complexity sphere decoding and application to interfering IEEE 802.15.3a piconets. ICC 2004: 2864-2868 |
| c72 | | Chao Cheng, Keshab K. Parhi: Hardware efficient fast parallel FIR filter structures based on iterated short convolution. ISCAS (3) 2004: 361-364 |
| c71 | | Ebrahim Saberinia, Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi: Pulsed OFDM modulation for ultra wideband communications. ISCAS (5) 2004: 369-392 |
| c70 | | Jun Tang, Ahmed H. Tewfik, Keshab K. Parhi: High performance solution for interfering UWB piconets with reduced complexity sphere decoding. ISCAS (5) 2004: 377-380 |
| c69 | | Keshab K. Parhi: Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders. ISCAS (2) 2004: 501-504 |
| c68 | | |
| 2003 | ||
| j62 | | Tong Zhang, Keshab K. Parhi: An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder. EURASIP J. Adv. Sig. Proc. 2003(6): 530-542 (2003) |
| j61 | | An-Yeu Wu, Ut-Va Koc, Keshab K. Parhi, Sergios Theodoridis: Editorial. EURASIP J. Adv. Sig. Proc. 2003(13): 1265-1267 (2003) |
| j60 | | Jun Jin Kong, Keshab K. Parhi: Interleaved Convolutional Code and Its Viterbi Decoder Architecture. EURASIP J. Adv. Sig. Proc. 2003(13): 1328-1334 (2003) |
| j59 | | Yanni Chen, Keshab K. Parhi: Low-Complexity Decoding of Block Turbo-Coded System with Antenna Diversity. EURASIP J. Adv. Sig. Proc. 2003(13): 1335-1345 (2003) |
| j58 | | Zhongfeng Wang, Keshab K. Parhi: High performance, high throughput turbo/SOVA decoder design. IEEE Transactions on Communications 51(4): 570-579 (2003) |
| j57 | | Vijay Sundararajan, Keshab K. Parhi: Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems. IEEE Transactions on Signal Processing 51(7): 1954-1965 (2003) |
| j56 | | T. Sansaloni, Javier Valls, Keshab K. Parhi: Digit-Serial Complex-Number Multipliers on FPGAs. VLSI Signal Processing 33(1-2): 105-115 (2003) |
| j55 | | Bibhudatta Sahoo, Keshab K. Parhi: A Low Power Correlator for CDMA Wireless Systems. VLSI Signal Processing 35(1): 105-112 (2003) |
| j54 | | Lijun Gao, Keshab K. Parhi, Jun Ma: Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters. VLSI Signal Processing 35(2): 119-135 (2003) |
| c67 | | Yanni Chen, Keshab K. Parhi: High throughput overlapped message passing for low density parity check codes. ACM Great Lakes Symposium on VLSI 2003: 245-248 |
| c66 | | Ji-Suk Park, Byeong-Kuk Kim, Jin-Gyun Chung, Keshab K. Parhi: High-speed tunable fractional-delay allpass filter structure. ISCAS (4) 2003: 165-168 |
| 2002 | ||
| j53 | | Martin Kuhlmann, Keshab K. Parhi: P-CORDIC: A Precomputation Based Rotation CORDIC Algorithm. EURASIP J. Adv. Sig. Proc. 2002(9): 936-943 (2002) |
| j52 | | Jin-Gyun Chung, Keshab K. Parhi: Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design. EURASIP J. Adv. Sig. Proc. 2002(9): 944-953 (2002) |
| j51 | | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002) |
| j50 | | Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi: Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. VLSI Syst. 10(6): 902-912 (2002) |
| j49 | | William L. Freking, Keshab K. Parhi: Performance-Scalable Array Architectures for Modular Multiplication. VLSI Signal Processing 31(2): 101-116 (2002) |
| j48 | | Javier Valls, Martin Kuhlmann, Keshab K. Parhi: Evaluation of CORDIC Algorithms for FPGA Design. VLSI Signal Processing 32(3): 207-222 (2002) |
| c65 | | Tong Zhang, Keshab K. Parhi: On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. ACM Great Lakes Symposium on VLSI 2002: 89-93 |
| c64 | | Yanni Chen, Keshab K. Parhi: A very low complexity soft decoding of space-time block codes. ICASSP 2002: 2693-2696 |
| c63 | | Zhipei Chi, Keshab K. Parhi: High speed algorithm and VLSI architecture design for decoding BCH product codes. ICASSP 2002: 3089-3092 |
| c62 | | Sang-Min Kim, Jin-Gyun Chung, Keshab K. Parhi: Design of low error CSD fixed-width multiplier. ISCAS (1) 2002: 69-72 |
| c61 | | Gunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi: High-speed add-compare-select units using locally self-resetting CMOS. ISCAS (1) 2002: 889-892 |
| c60 | | Zhipei Chi, Keshab K. Parhi: High speed VLSI architecture design for block turbo decoder. ISCAS (1) 2002: 901-904 |
| 2001 | ||
| j47 | | Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi: Vector processing of wavelet coefficients for robust image denoising. Image Vision Comput. 19(7): 435-450 (2001) |
| j46 | | Tong Zhang, Keshab K. Parhi: Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. IEEE Trans. Computers 50(7): 734-749 (2001) |
| j45 | | Jun Ma, Keshab K. Parhi, Ed F. Deprettere: A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms. IEEE Transactions on Signal Processing 49(2): 424-437 (2001) |
| j44 | | Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi: Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders. VLSI Signal Processing 29(3): 209-221 (2001) |
| c59 | | Lijun Gao, Keshab K. Parhi: Models for power consumption and power grid noise due to datapath transition activity. ACM Great Lakes Symposium on VLSI 2001: 121-126 |
| c58 | | Zhipei Chi, Leilei Song, Keshab K. Parhi: A study on the performance, complexity tradeoffs of block turbo decoder design. ISCAS (4) 2001: 65-68 |
| c57 | | Tong Zhang, Zhongfeng Wang, Keshab K. Parhi: On finite precision implementation of low density parity check codes decoder. ISCAS (4) 2001: 202-205 |
| c56 | | Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy efficient signaling in DSM CMOS technology. ISCAS (5) 2001: 411-414 |
| c55 | | Lijun Gao, Keshab K. Parhi: Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec. ISCAS (4) 2001: 574-577 |
| c54 | | Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy Efficient Signaling in Deep Submicron CMOS Technology. ISQED 2001: 319-324 |
| 2000 | ||
| j43 | | Janardhan H. Satyanarayana, Keshab K. Parhi: Power Estimation of Digital Data Paths Using HEAT. IEEE Design & Test of Computers 17(2): 101-110 (2000) |
| j42 | | Jun Ma, Keshab K. Parhi, Ed F. Deprettere: Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming. IEEE Transactions on Signal Processing 48(8): 2414-2431 (2000) |
| j41 | | Jun Ma, Keshab K. Parhi, Gerben J. Hekstra, Ed F. Deprettere: Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations. IEEE Transactions on Signal Processing 48(9): 2712-2716 (2000) |
| j40 | | Janardhan H. Satyanarayana, Keshab K. Parhi: Theoretical analysis of word-level switching activity in the presence of glitching and correlation. IEEE Trans. VLSI Syst. 8(2): 148-159 (2000) |
| j39 | | Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani: Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. IEEE Trans. VLSI Syst. 8(2): 160-172 (2000) |
| j38 | | Ahmed F. Shalash, Keshab K. Parhi: Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications. VLSI Signal Processing 25(3): 199-213 (2000) |
| c53 | | William L. Freking, Keshab K. Parhi: Performance-Scalable Array Architectures for Modular Multiplication. ASAP 2000: 149- |
| c52 | | |
| c51 | | Vijay Sundararajan, Keshab K. Parhi: Synthesis of low power folded programmable coefficient FIR digital filters (short paper). ASP-DAC 2000: 153-156 |
| c50 | | Vijay Sundararajan, Keshab K. Parhi: Data transmission over a bus with peak-limited transition activity. ASP-DAC 2000: 221-224 |
| c49 | | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664 |
| c48 | | Vijay Sundararajan, Keshab K. Parhi: Reducing bus transition activity by limited weight coding with codeword slimming. ACM Great Lakes Symposium on VLSI 2000: 13-16 |
| c47 | | Bibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi: A low-power correlator. ACM Great Lakes Symposium on VLSI 2000: 153-155 |
| 1999 | ||
| j37 | | Ahmed F. Shalash, Keshab K. Parhi: Multidimensional carrierless AM/PM systems for digital subscriber loops. IEEE Transactions on Communications 47(11): 1655-1667 (1999) |
| j36 | | Tracy C. Denk, Keshab K. Parhi: Two-dimensional retiming [VLSI design]. IEEE Trans. VLSI Syst. 7(2): 198-211 (1999) |
| j35 | | Keshab K. Parhi: Low-energy CSMT carry generators and binary adders. IEEE Trans. VLSI Syst. 7(4): 450-462 (1999) |
| j34 | | Hosahalli R. Srinivas, Keshab K. Parhi: A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture. VLSI Signal Processing 21(1): 37-60 (1999) |
| c46 | | Vijay Sundararajan, Keshab K. Parhi: Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. ARVLSI 1999: 170-185 |
| c45 | | Vijay Sundararajan, Keshab K. Parhi: Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. DAC 1999: 72-75 |
| c44 | | Janardhan H. Satyanarayana, Keshab K. Parhi: Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation. Great Lakes Symposium on VLSI 1999: 46-49 |
| c43 | | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6 |
| c42 | | William L. Freking, Keshab K. Parhi: A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations. ICCD 1999: 80- |
| c41 | | Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi: Efficient Crosstalk Estimation. ICCD 1999: 266- |
| c40 | | Zhipei Chi, Jun Ma, Keshab K. Parhi: Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures. ISCAS (3) 1999: 49-53 |
| c39 | | Leilei Song, Keshab K. Parhi: Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm. ISCAS (1) 1999: 84-89 |
| c38 | | S. Summerfield, Zhongfeng Wang, Keshab K. Parhi: Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ISCAS (3) 1999: 343-346 |
| c37 | | Jun Ma, Keshab K. Parhi, Ed F. Deprettere: Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. ISCAS (3) 1999: 347-350 |
| c36 | | William L. Freking, Keshab K. Parhi: Parallel modular multiplication with application to VLSI RSA implementation. ISCAS (1) 1999: 490-495 |
| c35 | | Leilei Song, Keshab K. Parhi: Low-complexity modified Mastrovito multipliers over finite fields GF(2M). ISCAS (1) 1999: 508-512 |
| c34 | | Ahmed F. Shalash, Keshab K. Parhi: Multiple access over wireline channels using orthogonal signaling. ISCAS (4) 1999: 580-583 |
| c33 | | Vijay Sundararajan, Keshab K. Parhi: Low power synthesis of dual threshold voltage CMOS VLSI circuits. ISLPED 1999: 139-144 |
| 1998 | ||
| j33 | | Luis A. Montalvo, Keshab K. Parhi, Alain Guyot: New Svoboda-Tung Division. IEEE Trans. Computers 47(9): 1014-1020 (1998) |
| j32 | | S. K. Jain, Leilei Song, Keshab K. Parhi: Efficient semisystolic architectures for finite-field arithmetic. IEEE Trans. VLSI Syst. 6(1): 101-113 (1998) |
| j31 | | K. Ito, Lori E. Lucke, Keshab K. Parhi: ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. VLSI Syst. 6(4): 582-594 (1998) |
| j30 | | Tracy C. Denk, Keshab K. Parhi: Synthesis of folded pipelined architectures for multirate DSP algorithms. IEEE Trans. VLSI Syst. 6(4): 595-607 (1998) |
| j29 | | Keshab K. Parhi, Valerie E. Taylor: Guest Editors' Introduction. VLSI Signal Processing 19(2): 83 (1998) |
| j28 | | Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. VLSI Signal Processing 19(3): 243-256 (1998) |
| c32 | | Ashish Karandikar, Keshab K. Parhi: Low power SRAM design using hierarchical divided bit-line approach. ICCD 1998: 82-88 |
| c31 | | Martin Kuhlmann, Keshab K. Parhi: Fast low-power shared division and square-root architecture. ICCD 1998: 128-135 |
| c30 | | Yun-Nan Chang, Keshab K. Parhi: High-performance digit-serial complex-number multiplier-accumulator. ICCD 1998: 211-213 |
| 1997 | ||
| j27 | | Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo: Radix 2 Division with Over-Redundant Quotient Selection. IEEE Trans. Computers 46(1): 85-92 (1997) |
| j26 | | Bin Fu, Keshab K. Parhi: Generalized multiplication-free arithmetic codes. IEEE Transactions on Communications 45(5): 497-501 (1997) |
| j25 | | Kalavai J. Raghunath, Keshab K. Parhi: Finite-precision error analysis of QRD-RLS and STAR-RLS adaptive filters. IEEE Transactions on Signal Processing 45(5): 1193-1209 (1997) |
| j24 | | Keshab K. Parhi, Takao Nishitani, Hironori Yamauchi: Guest Editors' Introduction. VLSI Signal Processing 16(1): 5-7 (1997) |
| j23 | | Kazuhito Ito, Keshab K. Parhi: A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. VLSI Signal Processing 16(1): 57-72 (1997) |
| j22 | | David A. Parker, Keshab K. Parhi: Low-Area/Power Parallel FIR Digital Filter Implementations. VLSI Signal Processing 17(1): 75-92 (1997) |
| c29 | | Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi: Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD 1997: 186-195 |
| c28 | | |
| c27 | | Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi: A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers. ICIP (1) 1997: 632-635 |
| 1996 | ||
| j21 | | Kalavai J. Raghunath, Keshab K. Parhi: Pipelined RLS adaptive filtering using scaled tangent rotations (STAR). IEEE Transactions on Signal Processing 44(10): 2591-2604 (1996) |
| j20 | | Tracy C. Denk, Keshab K. Parhi: Lower bounds on memory requirements for statically scheduled DSP programs. VLSI Signal Processing 12(3): 247-264 (1996) |
| c26 | | |
| c25 | | David A. Parker, Keshab K. Parhi: Area-Efficient Parallel FIR Digital Filter Implementations. ASAP 1996: 93-111 |
| c24 | | Janardhan H. Satyanarayana, Keshab K. Parhi: HEAT: Hierarchical Energy Analysis Tool. DAC 1996: 9-14 |
| c23 | | Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI 1996: 2-7 |
| c22 | | Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang: Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ICCD 1996: 492-499 |
| 1995 | ||
| j19 | | Hosahalli R. Srinivas, Keshab K. Parhi: A Fast Radix-4 Division Algorithm and Its Architecture. IEEE Trans. Computers 44(6): 826-831 (1995) |
| j18 | | Ching-Yi Wang, Keshab K. Parhi: High-level DSP synthesis using concurrent transformations, scheduling, and allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 274-295 (1995) |
| j17 | | Naresh R. Shanbhag, Keshab K. Parhi: Pipelined adaptive DFE architectures using relaxed look-ahead. IEEE Transactions on Signal Processing 43(6): 1368-1385 (1995) |
| j16 | | Keshab K. Parhi: High-level algorithm and architecture transformations for DSP synthesis. VLSI Signal Processing 9(1-2): 121-143 (1995) |
| j15 | | Ching-Yi Wang, Keshab K. Parhi: Resource-constrained loop list scheduler for DSP algorithms. VLSI Signal Processing 11(1-2): 75-96 (1995) |
| j14 | | Kazuhito Ito, Keshab K. Parhi: Determining the minimum iteration period of an algorithm. VLSI Signal Processing 11(3): 229-244 (1995) |
| c21 | | Hosahalli R. Srinivas, Keshab K. Parhi: A floating point radix 2 shared division/square root chip. ICCD 1995: 472-478 |
| c20 | | Jin-Gyun Chung, Keshab K. Parhi: Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain. ISCAS 1995: 77-80 |
| c19 | | |
| c18 | | |
| c17 | | |
| c16 | | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi: A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging. VLSI Design 1995: 398-402 |
| 1994 | ||
| j13 | | Keshab K. Parhi, Frank H. Wu, Kalyan Genesan: Sequential and Parallel Neural Network Vector Quantizers. IEEE Trans. Computers 43(1): 104-109 (1994) |
| j12 | | Jin-Gyun Chung, Keshab K. Parhi: Pipelining of lattice IIR digital filters. IEEE Transactions on Signal Processing 42(4): 751-761 (1994) |
| j11 | | Lori E. Lucke, Keshab K. Parhi: Parallel processing architectures for rank order and stack filters. IEEE Transactions on Signal Processing 42(5): 1178-1189 (1994) |
| j10 | | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi: A C-testable carry-free divider. IEEE Trans. VLSI Syst. 2(4): 472-488 (1994) |
| c15 | | Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi: Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD 1994: 322-329 |
| c14 | | Tracy C. Denk, Keshab K. Parhi: Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing. ISCAS 1994: 77-80 |
| c13 | | |
| c12 | | Keshab K. Parhi: Calculation of Minimum Number of Registers in Arbitrary Life Time Chart. VLSI Design 1994: 83-86 |
| 1993 | ||
| j9 | | Lori E. Lucke, Keshab K. Parhi: Data-flow transformations for critical path time reduction in high-level DSP synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1063-1068 (1993) |
| j8 | | Naresh R. Shanbhag, Keshab K. Parhi: A pipelined adaptive lattice filter architecture. IEEE Transactions on Signal Processing 41(5): 1925-1939 (1993) |
| j7 | | Kalavai J. Raghunath, Keshab K. Parhi: Parallel adaptive decision feedback equalizers. IEEE Transactions on Signal Processing 41(5): 1956-1961 (1993) |
| j6 | | Keshab K. Parhi, Takao Nishitani: VLSI architectures for discrete wavelet transforms. IEEE Trans. VLSI Syst. 1(2): 191-202 (1993) |
| c11 | | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi: A C-Testable Carry-Free Divider. ICCD 1993: 206-213 |
| c10 | | |
| c9 | | Naresh R. Shanbhag, Keshab K. Parhi: Roundoff error analysis of the pipelined ADPCM coder. ISCAS 1993: 886-889 |
| c8 | | Ching-Yi Wang, Keshab K. Parhi: Loop List Scheduler for DSP Algorithms under Resource Consraints. ISCAS 1993: 1662-1665 |
| c7 | | Keshab K. Parhi, Takao Nishitani: Folded VLSI Architectures for Discrete Wavelet Transforms. ISCAS 1993: 1734-1737 |
| c6 | | Naresh R. Shanbhag, Keshab K. Parhi: A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS 1993: 1956-1958 |
| c5 | | Kalavai J. Raghunath, Keshab K. Parhi: High Speed RLS Using Scaled Tangent Rotations (STAR). ISCAS 1993: 1959-1962 |
| c4 | | Gireesh Shrimali, Keshab K. Parhi: High-Speed Arithmetic Coder/Decoder Architectures. PPSC 1993: 1025-1032 |
| 1992 | ||
| j5 | | Keshab K. Parhi: Video data format converters using minimum number of registers. IEEE Trans. Circuits Syst. Video Techn. 2(2): 255-267 (1992) |
| j4 | | Hosahalli R. Srinivas, Keshab K. Parhi: High-speed VLSI arithmetic processor architectures using hybrid number representation. VLSI Signal Processing 4(2-3): 177-198 (1992) |
| 1991 | ||
| j3 | | Keshab K. Parhi, David G. Messerschmitt: Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding. IEEE Trans. Computers 40(2): 178-195 (1991) |
| j2 | | Keshab K. Parhi: Pipelining in dynamic programming architectures. IEEE Transactions on Signal Processing 39(6): 1442-1450 (1991) |
| j1 | | Keshab K. Parhi: Finite word effects in pipelined recursive filters. IEEE Transactions on Signal Processing 39(6): 1450-1454 (1991) |
| c3 | | Hosahalli R. Srinivas, Keshab K. Parhi: High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation. ICCD 1991: 564-571 |
| 1989 | ||
| c2 | | Keshab K. Parhi, David G. Messerschmitt: Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding. ICPP (1) 1989: 209-216 |
| c1 | | Rajiv Ramaswami, Keshab K. Parhi: Distributed Scheduling of Broadcasts in a Radio Network. INFOCOM 1989: 497-504 |
Colors in the list of coauthors
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