In-Cheol Park

Bongjin Kim, Injae Yoo, In-Cheol Park: Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. IEEE Trans. on Circuits and Systems 60-II(3): 162-166 (2013)

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park: A 3Gb/s 2.08mm² 100b error-correcting BCH decoder in 0.13µm CMOS process. ASP-DAC 2013: 85-86

Injae Yoo, Bongjin Kim, In-Cheol Park: Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. IEEE Communications Letters 16(12): 2048-2051 (2012)

Byeong Yong Kong, In-Cheol Park: FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1169-1179 (2012)

Kangwoo Park, In-Cheol Park: Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. IEEE Trans. VLSI Syst. 20(10): 1919-1923 (2012)

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park: Small-area parallel syndrome calculation for strong BCH decoding. ICASSP 2012: 1609-1612

Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park: 6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. ISSCC 2012: 426-428

Injae Yoo, In-Cheol Park: SNR-Adaptive Input Quantization for Turbo Decoding. VTC Spring 2012: 1-5

Tae-Hwan Kim, In-Cheol Park: Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration. IEICE Transactions 94-B(9): 2677-2680 (2011)

Youngjoo Lee, Hoyoung Yoo, In-Cheol Park: Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. IEEE Trans. on Circuits and Systems 58-II(8): 522-526 (2011)

Bongjin Kim, In-Cheol Park: QC-LDPC Decoding Architecture based on Stride Scheduling. ISCAS 2011: 1319-1322

In-Cheol Park, Tae-Hwan Kim: Multiplier-less and Table-less Linear Approximation for Square-Related Functions. IEICE Transactions 93-D(11): 2979-2988 (2010)

Tae-Hwan Kim, In-Cheol Park: High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search. IEEE Trans. on Circuits and Systems 57-I(7): 1756-1766 (2010)

Jinook Song, In-Cheol Park: Spur-Free MASH Delta-Sigma Modulation. IEEE Trans. on Circuits and Systems 57-I(9): 2426-2437 (2010)

Tae-Hwan Kim, In-Cheol Park: Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding. IEEE Trans. on Circuits and Systems 57-I(10): 2753-2761 (2010)

Minsoo Rhu, In-Cheol Park: Optimization of Arithmetic Coding for JPEG2000. IEEE Trans. Circuits Syst. Video Techn. 20(3): 446-451 (2010)

Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park: Design of a Scalable and Programmable Sound Synthesizer. IEEE Trans. VLSI Syst. 18(6): 875-886 (2010)

Tae-Hwan Kim, In-Cheol Park: A 2.6Gb/s 1.56mm² near-optimal MIMO detector in 0.18µm CMOS. CICC 2010: 1-4

Youngjoo Lee, Goeun Lim, In-Cheol Park: Low-complex BPSK demodulation using absolute comparison. ICECS 2010: 1080-1083

Bongjin Kim, Hasan Ahmed, In-Cheol Park: Dual-rail decoding of low-density parity-check codes. ISCAS 2010: 477-480

Youngjoo Lee, In-Cheol Park: Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters. ISCAS 2010: 1464-1467

Kangwoo Park, In-Cheol Park: Low-complexity tone reservation method for PAPR reduction of OFDM systems. ISCAS 2010: 2147-2150

Tae-Hwan Kim, In-Cheol Park: Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. ISLPED 2010: 231-236

Ji-Hoon Kim, In-Cheol Park: Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. IEEE Trans. on Circuits and Systems 56-II(1): 81-85 (2009)

Jinook Song, In-Cheol Park: Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines. IEEE Trans. on Circuits and Systems 56-II(12): 916-920 (2009)

Ji-Hoon Kim, In-Cheol Park: A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. CICC 2009: 487-490

Tae-Hwan Kim, In-Cheol Park: Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. GLOBECOM 2009: 1-6

In-Cheol Park, Tae-Hwan Kim: Multiplier-less and table-less linear approximation for square and square-root. ICCD 2009: 378-383

Minsoo Rhu, In-Cheol Park: Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. ICIP 2009: 2665-2668

Minsoo Rhu, In-Cheol Park: Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. ICIP 2009: 2673-2676

Jinook Song, In-Cheol Park: Novel Pipelined DWT Architecture for Dual-line Scan. ISCAS 2009: 373-376

Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park: A Scalable and Programmable Sound Synthesizer. ISCAS 2009: 1855-1858

Kangwoo Park, In-Cheol Park: Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking. ISCAS 2009: 1891-1894

Minsoo Rhu, In-Cheol Park: A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. SiPS 2009: 243-248

Jeong-Ho Han, In-Cheol Park: FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 958-962 (2008)

Ji-Hoon Kim, In-Cheol Park: Double-Binary Circular Turbo Decoding Based on Border Metric Encoding. IEEE Trans. on Circuits and Systems 55-II(1): 79-83 (2008)

Tae-Hwan Kim, In-Cheol Park: Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. IEEE Trans. VLSI Syst. 16(12): 1620-1630 (2008)

Ji-Hoon Kim, In-Cheol Park: Duo-binary circular turbo decoder based on border metric encoding for WiMAX. ASP-DAC 2008: 109-110

Tae-Hwan Kim, In-Cheol Park: Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. ASP-DAC 2008: 111-112

Jeong-Ho Han, In-Cheol Park: Digital filter synthesis considering multiple adder graphs for a coefficient. ICCD 2008: 315-320

WonHee Son, In-Cheol Park: Prediction-based real-time CABAC decoder for high definition H.264/AVC. ISCAS 2008: 33-36

Jeong-Sup Lee, In-Cheol Park: Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS 2008: 236-239

Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park: Fast frequency acquisition all-digital PLL using PVT calibration. ISCAS 2008: 2625-2628

Tae-Hwan Kim, In-Cheol Park: Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. VTC Spring 2008: 1186-1190

Chung-Hyo Kim, In-Cheol Park: Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction. IEICE Transactions 90-D(2): 609-612 (2007)

Ji-Hoon Kim, In-Cheol Park: Long-Point FFT Processing Based on Twiddle Factor Table Reduction. IEICE Transactions 90-A(11): 2526-2532 (2007)

Myoung-Cheol Shin, In-Cheol Park: SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. IEEE Trans. VLSI Syst. 15(7): 801-810 (2007)

In-Cheol Park, WonHee Son, Ji-Hoon Kim: Twiddle factor transformation for pipelined FFT processing. ICCD 2007: 1-6

Se-Hyeon Kang, In-Cheol Park: High Speed Sphere Decoding Based on Vertically Incremental Computation. ISCAS 2007: 665-668

Ji-Hoon Kim, In-Cheol Park: Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. ISCAS 2007: 1325-1328

Jung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol Park: Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. ISCAS 2007: 3984-3987

Tae-Hwan Kim, In-Cheol Park: Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems. SiPS 2007: 193-198

Se-Hyeon Kang, In-Cheol Park: Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. VTC Spring 2007: 2384-2388

Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park: Low-Power Hybrid Turbo Decoding Based on Reverse Calculation. IEICE Transactions 89-A(3): 782-789 (2006)

Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park: Low-power hybrid turbo decoding based on reverse calculation. ISCAS 2006

Chung-Hyo Kim, In-Cheol Park: High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. ISCAS 2006

Kimo Kim, In-Cheol Park: Combined image signal processing for CMOS image sensors. ISCAS 2006

Dong-Soo Lee, In-Cheol Park: A Low-Complexity Stopping Criterion for Iterative Turbo Decoding. IEICE Transactions 88-B(1): 399-401 (2005)

Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park: Performance enhancement of embedded software based on new register allocation technique. Microprocessors and Microsystems 29(4): 177-187 (2005)

Hyeong-Ju Kang, In-Cheol Park: SAT-based unbounded symbolic model checking. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 129-140 (2005)

Dong-Soo Lee, In-Cheol Park: Low-power log-MAP turbo decoding based on reduced metric memory access. ISCAS (4) 2005: 3167-3170

In-Cheol Park, Se-Hyeon Kang: Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) 2005: 5778-5781

Hyun-Yong Lee, In-Cheol Park: A fast Reed-Solomon Product-Code decoder without redundant computations. ISCAS (2) 2004: 381-384

Se-Hyeon Kang, In-Cheol Park: Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. ISCAS (2) 2004: 397-400

Sung-Won Lee, In-Cheol Park: Quadrature direct digital frequency synthesis using fine-grain angle rotation. ISCAS (2) 2004: 709-712

Jong-Yeol Lee, In-Cheol Park: Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 1-14 (2003)

Hyeong-Ju Kang, In-Cheol Park: SAT-based unbounded symbolic model checking. DAC 2003: 840-843

In-Cheol Park, Se-Hyeon Kang, Yongseok Yi: Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. ICCAD 2003: 138-141

Sung-Won Lee, In-Cheol Park: Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. ICME 2003: 849-852

Sang-Chul Moon, In-Cheol Park: Area-efficient memory-based architecture for FFT processing. ISCAS (5) 2003: 101-104

Seong-Il Park, In-Cheol Park: History-based memory mode prediction for improving memory performance. ISCAS (5) 2003: 185-188

Hyeong-Ju Kang, In-Cheol Park: Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) 2003: 265-268

Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park: A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) 2003: 748-751

Hyung Ki Ahn, In-Cheol Park, Beomsup Kim: A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) 2003: 797-800

Jae Hoon Shim, In-Cheol Park, Beomsup Kim: A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) 2003: 1025-1028

Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung: Interface synthesis between software chip model and target board. Journal of Systems Architecture 48(1-3): 49-57 (2002)

In-Cheol Park, Hyeong-Ju Kang: Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1525-1529 (2002)

Jong-Yeol Lee, In-Cheol Park: Timed compiled-code simulation of embedded software for performance analysis of SOC design. DAC 2002: 293-298

Hyeong-Ju Kang, In-Cheol Park: A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. ICASSP 2002: 3180-3183

Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park: Area-efficient digital baseband module for Bluetooth wireless communications. ISCAS (5) 2002: 729-732

Sung-Won Lee, In-Cheol Park: Low cost floating-point unit design for audio applications. ISCAS (1) 2002: 869-872

Hansoo Kim, In-Cheol Park: High-performance and low-power memory-interface architecture for video processing applications. IEEE Trans. Circuits Syst. Video Techn. 11(11): 1160-1170 (2001)

Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung: Low-power high-level synthesis using latches. ASP-DAC 2001: 462-466

In-Cheol Park, Hyeong-Ju Kang: Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC 2001: 468-473

Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park: An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ICCD 2001: 511-512

Jong-Yeol Lee, In-Cheol Park: Global variable localization and transformation for hardware synthesis from high-level programming language description. ISCAS (5) 2001: 13-16

Sung-Won Lee, In-Cheol Park: A low-power variable length decoder based on successive decoding of shoft codewords. ISCAS (4) 2001: 582-585

Hyeong-Ju Kang, In-Cheol Park: Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) 2001: 693-696

Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung: MetaCore: an application-specific programmable DSP development system. IEEE Trans. VLSI Syst. 8(2): 173-183 (2000)

Young-Su Kwon, In-Cheol Park, Chong-Min Kyung: A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. ASP-DAC 2000: 559-564

Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park: FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD 2000: 51-54

Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung: Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. ICCD 2000: 519-524

Young-Su Kwon, In-Cheol Park, Chong-Min Kyung: Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. ICIP 2000: 191-194

Hansoo Kim, In-Cheol Park: Array address translation for SDRAM-based video processing applications. VCIP 2000: 922-931

Myoung-Cheol Shin, In-Cheol Park: Optimal down-conversion in compressed DCT domain with minimal operations. VCIP 2000: 1613-1620

S. Lee, In-Cheol Park, Chong-Min Kyung: Path-based branch prediction using signature analysis. Microprocessors and Microsystems - Embedded Hardware Design 23(8-9): 527-536 (1999)

Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Synthesis of Application Specific Instructions for Embedded DSP Software. IEEE Trans. Computers 48(6): 603-614 (1999)

Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung: A New Single-Clock Flip-Clop for Half-Swing Clocking. ASP-DAC 1999: 117-120

Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. ASP-DAC 1999: 157-160

You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung: Verification of a Microprocessor Using Real World Applications. DAC 1999: 181-184

Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung: Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. DAC 1999: 939-944

You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung: Customization of a CISC Processor Core for Low-Power Applications. ICCD 1999: 152-

Bong-Il Park, In-Cheol Park, Chong-Min Kyung: A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ICCD 1999: 243-

Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung: Virtual Chip: Making Functional Models Work on Real Target Systems. DAC 1998: 170-173

Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung: MetaCore: An Application Specific DSP Development System. DAC 1998: 800-803

Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung: Multiple Behavior Module Synthesis Based on Selective Groupings. DATE 1998: 384-388

Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park: Synthesis of application specific instructions for embedded DSP software. ICCAD 1998: 665-671

Joon-Seo Yim, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung: Design Verification of Complex Microprocessors. Journal of Circuits, Systems, and Computers 7(4): 301-318 (1997)

Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung: Verification methodology of compatible microprocessors. ASP-DAC 1997: 173-180

Chong-Min Kyung, In-Cheol Park, Ho-Jun Song: Multi-project chip activities in Korea-IDEC perspective. ASP-DAC 1997: 353-357

Chong-Min Kyung, In-Cheol Park, Se-Kyoung Hong, K. S. Seong, B. S. Kong, S. J. Lee, Hoon Choi, S. R. Maeng, D. T. Kim, Jong-Sun Kim, S. H. Park, Y. J. Kang: HK386: an x86-compatible 32-bit CISC microprocessor. ASP-DAC 1997: 661-662

Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung: Single cycle access cache for the misaligned data and instruction prefetch. ASP-DAC 1997: 677-678

Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung: A C-Based RTL Design Verification Methodology for Complex Microprocessor. DAC 1997: 83-88

In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung: Two Complementary Approaches for Microcode Bit Optimization. IEEE Trans. Computers 43(2): 234-239 (1994)

In-Cheol Park, Chong-Min Kyung: FAMOS: an efficient scheduling algorithm for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1437-1448 (1993)

In-Cheol Park, Chong-Min Kyung: Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. DAC 1991: 680-685

Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung: An O(n³logn)-Heuristic for Microcode Bit Optimization. ICCAD 1990: 180-183