| 2011 | ||
|---|---|---|
| j4 | Joonseok Park, Pedro C. Diniz: Data Reorganization and Prefetching of Pointer-Based Data Structures. IEEE Design & Test of Computers 28(4): 38-47 (2011) | |
| 2009 | ||
| c17 | Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro: Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ARC 2009: 181-192 | |
| 2008 | ||
| j3 | Joon-Sang Park, Uichin Lee, Soon-Young Oh, Mario Gerla, Desmond S. Lun, Won Woo Ro, Joonseok Park: Delay Analysis of Car-to-Car Reliable Data Delivery Strategies Based on Data Mulling with Network Coding. IEICE Transactions 91-D(10): 2524-2527 (2008) | |
| 2007 | ||
| c16 | Joonseok Park, Pedro C. Diniz: Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. ARC 2007: 97-109 | |
| 2005 | ||
| j2 | Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler: Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. Microprocessors and Microsystems 29(2-3): 51-62 (2005) | |
| 2004 | ||
| j1 | Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee: Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Trans. Computers 53(11): 1420-1435 (2004) | |
| c15 | Nastaran Baradaran, Joonseok Park, Pedro C. Diniz: Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. FPL 2004: 1113-1115 | |
| c14 | Nastaran Baradaran, Joonseok Park, Pedro C. Diniz: Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks. FPT 2004: 145-152 | |
| c13 | Nastaran Baradaran, Pedro C. Diniz, Joonseok Park: Extending the Applicability of Scalar Replacement to Multiple Induction Variables. LCPC 2004: 455-469 | |
| 2003 | ||
| c12 | Pedro C. Diniz, Joonseok Park: Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. FCCM 2003: 207-217 | |
| c11 | K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. FCCM 2003: 296 | |
| c10 | Joonseok Park, Pedro C. Diniz: Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. FCCM 2003: 297-299 | |
| c9 | Pedro C. Diniz, Joonseok Park: Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. FPGA 2003: 242 | |
| c8 | K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz: Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323 | |
| 2002 | ||
| c7 | Pedro C. Diniz, Joonseok Park: Data reorganization engines for the next generation of system-on-a-chip FPGAs. FPGA 2002: 237-244 | |
| 2001 | ||
| c6 | Joonseok Park, Pedro C. Diniz: An External Memory Interface for FPGA-Based Computing Engines. FCCM 2001: 267-268 | |
| c5 | Pablo Moisset, Pedro C. Diniz, Joonseok Park: Matching and searching analysis for parallel hardware implementation on FPGAs. FPGA 2001: 125-133 | |
| c4 | Joonseok Park, Pedro C. Diniz: Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. ISSS 2001: 221-226 | |
| c3 | Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler: Bridging the Gap between Compilation and Synthesis in the DEFACTO System. LCPC 2001: 52-70 | |
| 2000 | ||
| c2 | Pedro C. Diniz, Joonseok Park: Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. FCCM 2000: 91-100 | |
| 1999 | ||
| c1 | Mary W. Hall, Peter M. Kogge, Jefferey G. Koller, Pedro C. Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John J. Granacki, Jay B. Brockman, Apoorv Srivastava, William C. Athas, Vincent W. Freeh, Jaewook Shin, Joonseok Park: Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture. SC 1999: 57 | |
Colors in the list of coauthors
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