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JoAnn M. Paul
2010 – today
- 2012
[j13]Mwaffaq Otoom, JoAnn M. Paul: Workload Mode Identification for Chip Heterogeneous Multiprocessors. International Journal of Parallel Programming 40(2): 184-224 (2012)- 2011
- [c23]Mwaffaq Otoom, JoAnn M. Paul: Capacity metric for chip heterogeneous multiprocessors. CODES+ISSS 2011: 207-216
- 2010
- [j12]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 59(10): 1402-1418 (2010)
2000 – 2009
- 2009
- [j11]JoAnn M. Paul, Mwaffaq Otoom, Marc Somers, Sean M. Pieper, Michael J. Schulte: The Emerging Landscape of Computer Performance Evaluation. Advances in Computers 75: 235-280 (2009)
- 2008
- [j10]F. Ryan Johnson, JoAnn M. Paul: Interrupt modeling for efficient high-level scheduler design space exploration. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
- [c22]Marc Somers, JoAnn M. Paul: Webpage-based benchmarks for mobile device design. ASP-DAC 2008: 795-800
- [c21]Mwaffaq Otoom, JoAnn M. Paul: Holistic design and caching in mobile computing. CODES+ISSS 2008: 115-120
- 2007
- [j9]Sean M. Pieper, JoAnn M. Paul, Michael J. Schulte: A New Era of Performance Evaluation. IEEE Computer 40(9): 23-30 (2007)
- [j8]JoAnn M. Paul, Brett H. Meyer: Amdahl's Law Revisited for Single Chip Systems. International Journal of Parallel Programming 35(2): 101-123 (2007)
- [c20]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS 2007: 69-74
- [c19]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas: Shared Resource Access Attributes for High-Level Contention Models. DAC 2007: 720-725
- 2006
- [j7]
- [j6]JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. VLSI Syst. 14(8): 868-880 (2006)
- 2005
- [j5]Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe: Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 54(6): 684-697 (2005)
- [j4]Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang: Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embedded Comput. Syst. 4(3): 500-528 (2005)
- [j3]JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy: High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. 10(3): 431-461 (2005)
- [c18]
- 2004
- [c17]JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS 2004: 54-59
- [c16]Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim: High level cache simulation for heterogeneous multiprocessors. DAC 2004: 287-292
- [c15]Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE 2004: 1144-1149
- 2003
- [c14]
- [c13]JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas: Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC 2003: 408-411
- [c12]Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas: Layered, Multi-Threaded, High-Level Performance Design. DATE 2003: 10954-10959
- 2002
- [c11]JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas: The design context of concurrent computation systems. CODES 2002: 19-24
- [c10]JoAnn M. Paul, Donald E. Thomas: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE 2002: 522-528
- [c9]JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas: Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS 2002
- [c8]Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul: System-Level Modeling of a Network Switch SoC. ISSS 2002: 62-67
- 2001
- [j2]Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas: Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. VLSI Syst. 9(6): 805-812 (2001)
- [c7]Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas: Modeling and evaluation of hardware/software designs. CODES 2001: 11-16
- [c6]JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas: Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS 2001: 262-267
- 2000
- [c5]JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: Frequency interleaving as a codesign scheduling paradigm. CODES 2000: 131-135
- [c4]JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC 2000: 390-395
1990 – 1999
- 1999
- [c3]Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber: Peer-based multithreaded executable co-specification. CODES 1999: 105-109
- 1996
- [j1]Marlin H. Mickle, JoAnn M. Paul: Load Balancing Using Heterogeneous Processors for Continuum Problems on a Mesh. J. Parallel Distrib. Comput. 39(1): 66-73 (1996)
- 1995
- [c2]Marlin H. Mickle, JoAnn M. Paul: Dynamic Communication and Architecture of Parallel Processors. Parallel and Distributed Computing and Systems 1995: 439-442
- [c1]Marlin H. Mickle, William G. Vogt, JoAnn M. Paul: The Dynamic Analysis of MIMD Architectures. Parallel and Distributed Computing and Systems 1995: 443-446
Coauthor Index
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last updated on 2012-12-02 21:17 CET by the dblp team