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Michael Payer
2000 – 2009
- 2003
[c8]- 2001
- [j2]Michael Payer: Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation). it+ti - Informationstechnik und Technische Informatik 43(1): 16-21 (2001)
- 2000
- [c7]
1990 – 1999
- 1995
- [c6]Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl: Model Checking in Industrial Hardware Design. DAC 1995: 298-303
- 1993
- [j1]J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy: The Siemens high-level synthesis system CALLAS. IEEE Trans. VLSI Syst. 1(3): 244-253 (1993)
- 1992
- [c5]J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer: Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274
- 1991
- [c4]Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer: Data-Path Synthesis Using Path Analysis. DAC 1991: 591-596
1980 – 1989
- 1989
- [c3]Michael Payer: Finite State Machine Theory as a Tool for Construction of Systolic Arrays. EUROCAST 1989: 212-224
- 1988
- [c2]Michael Payer: Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen. GI Jahrestagung (2) 1988: 174-190
- 1980
- [c1]
Coauthor Index
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last updated on 2012-12-02 20:42 CET by the dblp team