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 | 2012 | |
|---|---|---|
| c14 |      | Liang Tang, Jorgen Peddersen, Sri Parameswaran: A Rapid Methodology for Multi-mode Communication Circuit Generation. VLSI Design 2012: 203-208 |
| 2011 | ||
| c13 | | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran: CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD 2011: 126-133 |
| c12 | | Su Myat Min, Jorgen Peddersen, Sri Parameswaran: Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. VLSI Design 2011: 141-146 |
| 2010 | ||
| j3 | | Xin He, Jorgen Peddersen, Sri Parameswaran: LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. Design Autom. for Emb. Sys. 14(3): 231-263 (2010) |
| c11 | | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran: SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC 2010: 356-361 |
| c10 | | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran: DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE 2010: 496-501 |
| c9 | | Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran: Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE 2010: 920-925 |
| c8 | | Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran: RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC 2010: 137-144 |
| c7 | | Xin He, Jorgen Peddersen, Sri Parameswaran: Improved Architectures for Range Encoding in Packet Classification System. NCA 2010: 10-19 |
| c6 | | Karin Avnit, Arcot Sowmya, Jorgen Peddersen: ACS: Automatic Converter Synthesis for SoC Bus Protocols. TACAS 2010: 343-348 |
| 2009 | ||
| c5 | | Xin He, Jorgen Peddersen, Sri Parameswaran: LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS 2009: 137-146 |
| c4 | | Xin He, Jorgen Peddersen, Sri Parameswaran: LOP_RE: Range encoding for low power packet classification. LCN 2009: 137-144 |
| 2008 | ||
| j2 | | Jorgen Peddersen, Sri Parameswaran: Low-Impact Processor for Dynamic Runtime Power Management. IEEE Design & Test of Computers 25(1): 52-62 (2008) |
| j1 | | Jorgen Peddersen, Sri Parameswaran: Energy Driven Application Self-Adaptation at Run-time. JCP 3(3): 14-24 (2008) |
| 2007 | ||
| c3 | | Jorgen Peddersen, Sri Parameswaran: CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC 2007: 890-895 |
| c2 | | Jorgen Peddersen, Sri Parameswaran: Energy Driven Application SelfAdaptation. VLSI Design 2007: 385-390 |
| 2005 | ||
| c1 | | Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran: Rapid Embedded Hardware/Software System Generation. VLSI Design 2005: 111-116 |
| 1 | Jude Angelo Ambrose | |
| 2 | Karin Avnit | |
| 3 | Mohammad Shihabul Haque | |
| 4 | Xin He | |
| 5 | Aleksandar Ignjatovic | |
| 6 | Andhi Janapsatya | |
| 7 | Su Myat Min | |
| 8 | Sri Parameswaran | |
| 9 | Roshan G. Ragel | |
| 10 | Seng Lin Shee | |
| 11 | Arcot Sowmya | |
| 12 | Liang Tang |
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