Volnei A. Pedroni

Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao: A new hardware coprocessor for accelerating Notification-Oriented applications. FPT 2012: 257-260

Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni: A very efficient single-iteration oldest-out data sorter. ISCAS 2011: 2141-2144

Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni: Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart. ReConFig 2010: 127-131

Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.: An Improved GF(2) Matrix Inverter with Linear Time Complexity. ReConFig 2010: 322-327

Antonio Petraglia, Volnei A. Pedroni, Gert Cauwenberghs (Eds.): Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007. ACM 2007, isbn 978-1-59593-816-9

Volnei A. Pedroni: Phase sampling: a new approach to the design of LF direct digital frequency synthesizers. ISCAS 2006

Volnei A. Pedroni, Ricardo U. Pedroni: PLL-less clock multiplier with self-adjusting phase symmetry. ISCAS 2006

Volnei A. Pedroni: Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations. ISCAS (2) 2004: 585-588

Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni: Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs. ISCAS (1) 2004: 1088-1091

Volnei A. Pedroni: Teaching Design-Oriented VHDL. MSE 2003: 6-7

Volnei A. Pedroni: High-Resolution WTA-MAX Circuit for Large Networks. VLSI 2003: 150-154

Gert Cauwenberghs, Volnei A. Pedroni: A Charge-Based Parallel Analog Vector Quantizer. NIPS 1994: 779-787