| 2013 | ||
|---|---|---|
| j12 | Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi: On the design of modulo 2n + 1 dot product and generalized multiply-add units. Computers & Electrical Engineering 39(2): 410-419 (2013) | |
| 2012 | ||
| j11 | Isidoros Sideris, Kiamal Z. Pekmestzi: Cost Effective Protection Techniques for TCAM Memory Arrays. IEEE Trans. Computers 61(12): 1778-1788 (2012) | |
| j10 | Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. ACM Trans. Design Autom. Electr. Syst. 18(1): 11 (2012) | |
| j9 | Nicholas Axelos, Kiamal Z. Pekmestzi, Dimitris Gizopoulos: Efficient Memory Repair Using Cache-Based Redundancy. IEEE Trans. VLSI Syst. 20(12): 2278-2288 (2012) | |
| c27 | Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi: On the Design of Configurable Modulo 2n±1 Residue Generators. DSD 2012: 50-56 | |
| 2011 | ||
| j8 | Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi: High Performance and Area Efficient Flexible DSP Datapath Synthesis. IEEE Trans. VLSI Syst. 19(3): 429-442 (2011) | |
| c26 | Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos: On the Design of Modulo 2^n+1 Multipliers. DSD 2011: 453-459 | |
| 2010 | ||
| c25 | Nicholas Axelos, Kiamal Z. Pekmestzi: A bit level area aware cache-based architecture for memory repairs. IOLTS 2010: 154-158 | |
| c24 | Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. ISCAS 2010: 2598-2601 | |
| c23 | Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. ISVLSI 2010: 104-109 | |
| c22 | Nicholas Axelos, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos: A New Low-Power Soft-Error Tolerant SRAM Cell. ISVLSI 2010: 399-404 | |
| c21 | Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos: High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. ISVLSI 2010: 486-487 | |
| c20 | Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi: A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. PATMOS 2010: 73-83 | |
| c19 | Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi: A fast multiplier-less edge detection accelerator for FPGAs. SAC 2010: 510-515 | |
| c18 | Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi: A hardware peripheral for Java bytecodes translation acceleration. SAC 2010: 552-553 | |
| c17 | Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi: Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms. ICSAMOS 2010: 102-109 | |
| 2009 | ||
| j7 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. Integration 42(4): 486-503 (2009) | |
| j6 | Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: Extending an embedded RISC microprocessor for efficient translation based Java execution. Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 415-429 (2009) | |
| c16 | Sotirios Xydis, Ioannis S. Triantafyllou, George Economakos, Kiamal Z. Pekmestzi: Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. AHS 2009: 407-414 | |
| c15 | Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. ICECS 2009: 415-418 | |
| 2008 | ||
| j5 | Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: A predecoding technique for ILP exploitation in Java processors. Journal of Systems Architecture - Embedded Systems Design 54(7): 707-728 (2008) | |
| c14 | Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi: Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. AHS 2008: 346-353 | |
| c13 | Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou: A high-speed radix-4 multiplexer-based array multiplier. ACM Great Lakes Symposium on VLSI 2008: 115-118 | |
| c12 | Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos: A BISR Architecture for Embedded Memories. IOLTS 2008: 149-154 | |
| c11 | Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos: An instruction set extension for java bytecodes translation acceleration. ICSAMOS 2008: 116-123 | |
| 2007 | ||
| c10 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS 2007: 342-349 | |
| c9 | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. IOLTS 2007: 71-78 | |
| c8 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi: Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS 2007: 137-144 | |
| 2006 | ||
| c7 | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: A Large Scale Adaptable Multiplier for Cryptographic Applications. AHS 2006: 477-484 | |
| c6 | Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi: FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. ICCD 2006 | |
| c5 | P. Bougas, A. Tsirikos, K. Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi: Segmentation based design of serial parallel multipliers. ISCAS 2006 | |
| 2005 | ||
| j4 | Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi: A New Low Latency Parallel FIR Filter Scheme. VLSI Signal Processing 39(3): 313-322 (2005) | |
| c4 | E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi: Long Number Bit-Serial Squarers. IEEE Symposium on Computer Arithmetic 2005: 29-36 | |
| 2002 | ||
| j3 | Kiamal Z. Pekmestzi, Nikos K. Moshopoulos: A Systolic, High Speed Architecture for an RSA Cryptosystem. VLSI Signal Processing 32(3): 223-235 (2002) | |
| 2001 | ||
| j2 | Kiamal Z. Pekmestzi, Nikos K. Moshopoulos: A bit-interleaved systolic architecture for a high-speed RSA system. Integration 30(2): 169-175 (2001) | |
| c3 | Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi: On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms. ISC 2001: 248-265 | |
| c2 | Nikos K. Moshopoulos, Kiamal Z. Pekmestzi: A Novel Systolic Architecture for Efficient RSA Implementation. Public Key Cryptography 2001: 416-421 | |
| 2000 | ||
| j1 | Kiamal Z. Pekmestzi, Paraskevas Kalivas: Constant Number Serial Pipeline Multipliers. VLSI Signal Processing 26(3): 361-368 (2000) | |
| 1997 | ||
| c1 | George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas: Hardware compilation using attribute grammars. CHARME 1997: 273-290 | |
Colors in the list of coauthors
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