- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| c14 |      | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas: Heracles: a tool for fast RTL-based design space exploration of multicore processors. FPGA 2013: 125-134 |
| 2012 | ||
| c13 | | Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer: Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184 |
| 2011 | ||
| c12 | | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer: Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28 |
| c11 | | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas: Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. FPL 2011: 356-362 |
| c10 | | Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer: HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417 |
| 2010 | ||
| c9 | | Nirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind: A design flow based on modular refinement. MEMOCODE 2010: 11-20 |
| c8 | | Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer: Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE 2010: 69-72 |
| 2009 | ||
| j1 | | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. TRETS 2(3) (2009) |
| c7 | | Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer: Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281 |
| 2008 | ||
| c6 | | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 |
| c5 | | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 |
| 2007 | ||
| c4 | | |
| c3 | | Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan: Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. MEMOCODE 2007: 97-100 |
| 2006 | ||
| c2 | | Nirav Dave, Michael Pellauer, S. Gerding, Arvind: 802.11a transmitter: a case study in microarchitectural exploration. MEMOCODE 2006: 59-68 |
| 2005 | ||
| c1 | | Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil: Synthesis of synchronous assertions with guarded atomic actions. MEMOCODE 2005: 15-24 |
Data released under the ODC-BY 1.0 license — See also our legal information page