Lawrence T. Pileggi

Larry T. Pileggi, Lawrence T. Pillage

	2012
c130		Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman: A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4
c129		Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi: Statistical design and optimization for adaptive post-silicon tuning of MEMS filters. DAC 2012: 176-181
c128		Daniel Morris, David Bromberg, Jian-Gang (Jimmy) Zhu, Larry T. Pileggi: mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices. DAC 2012: 486-491
	2011
j35		Gokce Keskin, Jonathan Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi: Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. J. Solid-State Circuits 46(8): 1904-1918 (2011)
c127		Soner Yaldiz, V. Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno: Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC 2011: 1-4
c126		Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, SangBum Kim, Jonathan Proesel, Chung Lam: Post-silicon calibration of analog CMOS using phase-change memory cells. ESSCIRC 2011: 423-426
c125		Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi: Formal verification of phase-locked loops using reachability analysis and continuization. ICCAD 2011: 659-666
	2010
j34		Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler: Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 509-527 (2010)
c124		Gokce Keskin, Jonathan Proesel, Larry T. Pileggi: Statistical modeling and post manufacturing configuration for scaled analog CMOS. CICC 2010: 1-4
c123		Jonathan Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi: An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC 2010: 1-4
c122		Alyssa Bonnoit, Lawrence T. Pileggi: Reducing variability in chip-multiprocessors with adaptive body biasing. ISLPED 2010: 73-78
	2009
j33		Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd: Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 623-637 (2009)
c121		Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi: Creating an affordable 22nm node using design-lithography co-optimization. DAC 2009: 95-96
c120		Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi: SRAM parametric failure analysis. DAC 2009: 496-501
c119		Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi: Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. ISLPED 2009: 207-212
c118		Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi: Efficient statistical analysis of read timing failures in SRAM circuits. ISQED 2009: 617-621
	2008
j32		Xin Li, Yaping Zhan, Lawrence T. Pileggi: Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 831-843 (2008)
j31		Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi: Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1041-1054 (2008)
c117		Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi: Automated Testability Enhancements for Logic Brick Libraries. DATE 2008: 480-485
	2007
j30		Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi: Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 2-15 (2007)
j29		Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi: Asymptotic Probability Extraction for Nonnormal Performance Distributions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 16-37 (2007)
c116		Brian Taylor, Larry T. Pileggi: Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. DAC 2007: 344-349
c115		Xin Li, Lawrence T. Pileggi: Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits. DAC 2007: 928-933
c114		Jian Wang, Xin Li, Lawrence T. Pileggi: Parameterized Macromodeling for Analog System-Level Design Exploration. DAC 2007: 940-943
c113		Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi: Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007: 450-457
i2		Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. CoRR abs/0710.4654 (2007)
i1		Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS. CoRR abs/0710.4719 (2007)
	2006
j28		Xin Li, Jiayong Le, Lawrence T. Pileggi: Statistical Performance Modeling and Optimization. Foundations and Trends in Electronic Design Automation 1(4) (2006)
j27		Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra: IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1763-1776 (2006)
c112		Xin Li, Jiayong Le, Lawrence T. Pileggi: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. DAC 2006: 103-108
c111		Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi: Architecture-aware FPGA placement using metric embedding. DAC 2006: 460-465
c110		Kim Yaw Tong, Lawrence T. Pileggi: Synthesis of Regular Logic Bricks for Robust IC Design. ICCD 2006
	2005
j26		Peng Li, Lawrence T. Pileggi: Compact reduced-order modeling of weakly nonlinear analog and RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 184-203 (2005)
c109		Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma: Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC 2005: 77-82
c108		V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi: Design methodology for IC manufacturability based on regular logic-bricks. DAC 2005: 353-358
c107		Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi: OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. DAC 2005: 632-637
c106		Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS. DATE 2005: 164-169
c105		Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE 2005: 958-963
c104		Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang: Performance-centering optimization for system-level analog design exploration. ICCAD 2005: 422-429
c103		Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas: Projection-based performance modeling for inter/intra-die variations. ICCAD 2005: 721-727
c102		Xin Li, Peng Li, Lawrence T. Pileggi: Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. ICCAD 2005: 806-812
c101		Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi: Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD 2005: 844-851
c100		Peng Li, Yangdong Deng, Lawrence T. Pileggi: Temperature-Dependent Optimization of Cache Leakage Power Dissipation. ICCD 2005: 7-12
	2004
j25		Michael W. Beattie, Lawrence T. Pileggi: Parasitics extraction with multipole refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 288-292 (2004)
c99		Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd: ORACLE: optimization with recourse of analog circuits including layout extraction. DAC 2004: 151-154
c98		V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi: Routing architecture exploration for regular fabrics. DAC 2004: 204-207
c97		Jiayong Le, Xin Li, Lawrence T. Pileggi: STAC: statistical timing analysis with correlation. DAC 2004: 343-348
c96		Satrajit Gupta, Lawrence T. Pileggi: CHIME: coupled hierarchical inductance model evaluation. DAC 2004: 800-805
c95		Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi: A frequency relaxation approach for analog/RF system-level simulation. DAC 2004: 842-847
c94		Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi: Exploring Logic Block Granularity for Regular Fabrics. DATE 2004: 468-473
c93		Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi: An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE 2004: 1138-1143
c92		Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi: Asymptotic probability extraction for non-normal distributions of circuit performance. ICCAD 2004: 2-9
c91		Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi: A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD 2004: 275-282
c90		Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra: Efficient full-chip thermal modeling and analysis. ICCAD 2004: 319-326
c89		Peng Li, Lawrence T. Pileggi: Efficient harmonic balance simulation using multi-level frequency decomposition. ICCAD 2004: 677-682
c88		Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi: Robust analog/RF circuit design with projection-based posynomial modeling. ICCAD 2004: 855-862
c87		Radu Marculescu, Diana Marculescu, Larry T. Pileggi: Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. ICCD 2004: 168-173
	2003
j24		Hui Zheng, Byron Krauter, Lawrence T. Pileggi: Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Design & Test of Computers 20(3): 24-31 (2003)
j23		Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Global and local congestion optimization in technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 498-505 (2003)
j22		Peng Li, Lawrence T. Pileggi: Efficient per-nonlinearity distortion analysis for analog and RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1297-1309 (2003)
c86		Xin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi: A frequency separation macromodel for system-level simulation of RF circuits. ASP-DAC 2003: 891-896
c85		Peng Li, Lawrence T. Pileggi: Nonlinear distortion analysis via linear-centric models. ASP-DAC 2003: 897-903
c84		Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi: Fast, cheap and under control: the next implementation fabric. DAC 2003: 354-355
c83		Peng Li, Lawrence T. Pileggi: NORM: compact model order reduction of weakly nonlinear systems. DAC 2003: 472-477
c82		Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi: Analog and RF circuit macromodels for system-level analysis. DAC 2003: 478-483
c81		Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, K. Y. Tong: Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787
c80		Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi: Noise Macromodel for Radio Frequency Integrated Circuits. DATE 2003: 10150-10155
c79		Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Programmable Logic Block Architectures. DATE 2003: 11118-11119
c78		Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL 2003: 426-436
c77		Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI 2003: 7-10
c76		Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-Dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi: A fast simulation approach for inductive effects of VLSI interconnects. ACM Great Lakes Symposium on VLSI 2003: 108-111
c75		Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi: A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. ICCAD 2003: 454-462
c74		Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan: Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD 2003: 491-496
c73		Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi: An architectural exploration of via patterned gate arrays. ISPD 2003: 184-189
c72		E. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi: Power Comparison of Throughput Optimized IC Busses. ISVLSI 2003: 35-44
	2002
j21		Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: An analysis of the wire-load model uncertainty problem. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002)
j20		Emrah Acar, Florentin Dartu, Lawrence T. Pileggi: TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 605-616 (2002)
j19		Michael W. Beattie, Lawrence T. Pileggi: On-chip induction modeling: basics and advanced methods. IEEE Trans. VLSI Syst. 10(6): 712-729 (2002)
c71		Hui Zheng, Lawrence T. Pileggi: Modeling and analysis of regular symmetrically structured power/ground distribution networks. DAC 2002: 395-398
c70		Tao Lin, Michael W. Beattie, Lawrence T. Pileggi: On the efficacy of simplified 2D on-chip inductance models. DAC 2002: 757-762
c69		Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi: A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE 2002: 568-575
c68		Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE 2002: 628-633
c67		Peng Li, Lawrence T. Pileggi: A Linear-Centric Modeling Approach to Harmonic Balance Analysis. DATE 2002: 634-639
c66		Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Congestion-Aware Logic Synthesis. DATE 2002: 664-671
c65		Tao Lin, Michael W. Beattie, Lawrence T. Pileggi: On-Chip Inductance Models: 3D or Not 3D? DATE 2002: 1112
c64		Aneesh Koorapaty, Lawrence T. Pileggi: Modular, Fabric-Specific Synthesis for Programmable Architectures. FPL 2002: 132-141
c63		Tao Lin, Lawrence T. Pileggi: Throughput-driven IC communication fabric synthesis. ICCAD 2002: 274-279
c62		Hui Zheng, Lawrence T. Pileggi: Robust and passive model order reduction for circuits containing susceptance elements. ICCAD 2002: 761-766
c61		Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Understanding and addressing the impact of wiring congestion during technology mapping. ISPD 2002: 131-136
c60		Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi: Time-Domain Simulation of Variational Interconnect Models. ISQED 2002: 419-424
e1		Lawrence T. Pileggi, Andreas Kuehlmann (Eds.): Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002. ACM 2002, isbn 0-7803-7607-2
	2001
j18		Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi: Equipotential shells for efficient inductance extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 70-79 (2001)
c59		Michael W. Beattie, Lawrence T. Pileggi: Inductance 101: Modeling and Extraction. DAC 2001: 323-328
c58		Michael W. Beattie, Lawrence T. Pileggi: Modeling Magnetic Coupling for On-Chip Interconnect. DAC 2001: 335-340
c57		Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi: Min/max On-Chip Inductance Models and Delay Metrics. DAC 2001: 341-346
c56		Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731
c55		Michael W. Beattie, Lawrence T. Pileggi: Efficient inductance extraction via windowing. DATE 2001: 430-436
c54		Tao Lin, Lawrence T. Pileggi: RC(L) interconnect sizing with second order considerations via posynomial programming. ISPD 2001: 16-21
c53		Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: Overcoming wireload model uncertainty during physical design. ISPD 2001: 182-189
c52		Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu: Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED 2001: 431-436
	2000
c51		Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas: Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171
c50		Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer: Design closure (panel session): hope or hype? DAC 2000: 176-177
c49		Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: TACO: timing analysis with coupling. DAC 2000: 266-269
c48		Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi: Hierarchical Interconnect Circuit Models. ICCAD 2000: 215-221
	1999
j17		Mustafa Celik, Lawrence T. Pileggi: Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 293-300 (1999)
j16		Michael W. Beattie, Lawrence T. Pileggi: Error bounds for capacitance extraction via window techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 311-321 (1999)
c47		Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas: Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC 1999: 201-206
c46		Michael W. Beattie, Lawrence T. Pileggi: IC Analyses Including Extracted Inductance Models. DAC 1999: 915-920
c45		Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63
c44		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: Practical considerations for passive reduction of RLC circuits. ICCAD 1999: 214-220
c43		Michael W. Beattie, Lawrence T. Pileggi: Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. ICCAD 1999: 437-444
	1998
j15		Rony Kay, Lawrence T. Pileggi: EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 40-49 (1998)
j14		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 645-654 (1998)
j13		Rohini Gupta, John Willis, Lawrence T. Pileggi: Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. IEEE Trans. VLSI Syst. 6(3): 457-463 (1998)
c42		Rony Kay, Lawrence T. Pileggi: PRIMO: Probability Interpretation of Moments for Delay Calculation. DAC 1998: 463-468
c41		Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. DAC 1998: 469-472
c40		Florentin Dartu, Lawrence T. Pileggi: TETA: Transistor-Level Engine for Timing Analysis. DAC 1998: 595-598
c39		Tao Lin, Emrah Acar, Lawrence T. Pileggi: h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. ICCAD 1998: 19-25
c38		Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219
c37		Lawrence T. Pileggi: Timing metrics for physical design of deep submicron technologies. ISPD 1998: 28-33
	1997
j12		Rohini Gupta, Byron Krauter, Lawrence T. Pileggi: Transmission line synthesis via constrained multivariable optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 6-19 (1997)
j11		Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi: The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 95-104 (1997)
j10		Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 210-215 (1997)
j9		Noel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 867-881 (1997)
c36		Florentin Dartu, Lawrence T. Pileggi: Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51
c35		Michael W. Beattie, Lawrence T. Pileggi: Bounds for BEM Capacitance Extraction. DAC 1997: 133-136
c34		Zhijiang He, Mustafa Celik, Lawrence T. Pileggi: SPIE: Sparse Partial Inductance Extraction. DAC 1997: 137-140
c33		Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD 1997: 58-65
c32		Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273
c31		Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi: Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223
c30		Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229
c29		Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi: EWA: exact wiring-sizing algorithm. ISPD 1997: 178-185
	1996
j8		Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi: Domain characterization of transmission line models and analyses. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 184-193 (1996)
j7		Florentin Dartu, Noel Menezes, Lawrence T. Pileggi: Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 544-553 (1996)
j6		Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 691-701 (1996)
c28		Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi: A Sparse Image Method for BEM Capacitance Extraction. DAC 1996: 357-362
c27		Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi: RC-Interconnect Macromodels for Timing Simulation. DAC 1996: 544-547
c26		Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi: An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC 1996: 611-616
c25		Rohini Gupta, Byron Krauter, Lawrence T. Pileggi: On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. VLSI Design 1996: 150-155
	1995
c24		Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi: Transmission Line Synthesis. DAC 1995: 358-363
c23		Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. DAC 1995: 364-369
c22		Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695
c21		Byron Krauter, Lawrence T. Pileggi: Generating sparse partial inductance matrices with guaranteed stability. ICCAD 1995: 45-52
c20		Rohini Gupta, Lawrence T. Pileggi: Constrained multivariable optimization of transmission lines with general topologies. ICCAD 1995: 130-137
c19		Noel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD 1995: 144-151
c18		Lawrence T. Pileggi: Coping with RC(L) interconnect design headaches. ICCAD 1995: 246-253
	1994
j5		Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage: Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 729-736 (1994)
j4		Curtis L. Ratzlaff, Lawrence T. Pillage: RICE: rapid interconnect circuit evaluation using AWE. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 763-776 (1994)
j3		Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage: Time-domain macromodels for VLSI interconnect analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1257-1270 (1994)
j2		Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage: Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1526-1535 (1994)
c17		Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580
c16		Rohini Gupta, Lawrence T. Pillage: OTTER: Optimal Termination of Transmission Lines Excluding Radiation. DAC 1994: 640-645
c15		Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer: Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337
c14		Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage: RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425
c13		Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage: Domain Characterization of Transmission Line Models for Efficient Simulation. ICCD 1994: 558-562
	1993
c12		Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage: Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170
c11		Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh: Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. DAC 1993: 367-372
c10		S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, T. Savarino, Dean P. Neikirk, Lawrence T. Pillage: An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. ICCAD 1993: 58-65
	1992
c9		Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage: On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. DAC 1992: 207-212
c8		Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage: AWE macromodels of VLSI interconnect for circuit simulation. ICCAD 1992: 64-70
c7		Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage: ETA: electrical-level timing analysis. ICCAD 1992: 258-262
	1991
c6		Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage: RICE: Rapid Interconnect Circuit Evaluator. DAC 1991: 555-560
c5		Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage: Evaluating RC-Interconnect Using Moment-Matching Approximations. ICCAD 1991: 74-77
	1990
j1		Lawrence T. Pillage, Ronald A. Rohrer: Asymptotic waveform evaluation for timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 352-366 (1990)
c4		Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage: DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. ICCAD 1990: 546-549
	1989
c3		Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer: Efficient Final Placement Based on Nets-as-Points. DAC 1989: 578-581
c2		Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer: AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. DAC 1989: 634-637
	1988
c1		Lawrence T. Pillage, Ronald A. Rohrer: A Quadratic Metric with a Simple Solution Scheme for Initial Placement. DAC 1988: 324-329

Coauthor Index

Colors in the list of coauthors

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