R. Pires
List of publications from the DBLP Bibliography Server - FAQ
- CSB - MetaPress - Google - Bing - Yahoo
 | 2012 | |
|---|---|---|
| j3 |      | Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Wang Jiang Chau, Marius Strum: QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfig. Comp. 2012 (2012) |
| c8 | | Martha Johanna Sepúlveda, Wang Jiang Chau, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires: Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) 2012: 1449-1450 |
| c7 | | Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum: Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI 2012: 1-6 |
| i1 | | Ricardo Pires: A Common Evaluation Setting for Just.Ask, Open Ephyra and Aranea QA systems. CoRR abs/1205.1779 (2012) |
| 2011 | ||
| c6 | | Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum: Dynamic NoC-based architecture for MPSoC security implementation. SBCCI 2011: 197-202 |
| 2010 | ||
| j2 | | Johanna Sepúlveda, Ricardo Pires, Marius Strum, Wang Jiang Chau: Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Transactions on Computational Science 10: 187-201 (2010) |
| c5 | | Johanna Sepúlveda, Marius Strum, Wang Jiang Chau, Ricardo Pires: The LRD traffic impact on the NoC-based SoCs. SBCCI 2010: 97-102 |
| 2004 | ||
| j1 | | J. C. Wang, Paulo Sérgio Cardoso, Jose Artur Quilici Gonzalez, Marius Strum, Ricardo Pires: Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electronic Testing 20(4): 333-344 (2004) |
| 1998 | ||
| c4 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 |
| c3 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922 |
| c2 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340 |
| 1997 | ||
| c1 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165 |
Colors in the list of coauthors
Last update Sat May 18 20:33:41 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page