Peter Pirsch

Stefan Langemeyer, Peter Pirsch, Holger Blume: Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose. International Journal of Parallel Programming 41(2): 331-354 (2013)

Stefan Langemeyer, Peter Pirsch, Holger Blume: A FPGA architecture for real-time processing of variable-length FFTS. ICASSP 2011: 1705-1708

Christian Banz, Holger Blume, Peter Pirsch: Real-time semi-global matching disparity estimation on the GPU. ICCV Workshops 2011: 514-521

Stefan Langemeyer, Peter Pirsch, Holger Blume: Using SDRAMs for two-dimensional accesses of long 2ⁿ × 2^m-point FFTs and transposing. ICSAMOS 2011: 242-248

Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch: A Multi-Shared Register File Structure for VLIW Processors. Signal Processing Systems 58(2): 215-231 (2010)

Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch: A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ASAP 2010: 151-158

Holger Flatt, Holger Blume, Peter Pirsch: Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution. ReConFig 2010: 452-457

Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer: A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing. ICSAMOS 2010: 45-54

Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch: Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation. ICSAMOS 2010: 93-101

Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch: An Enhanced DMA Controller in SIMD Processors for Video Applications. ARCS 2009: 159-170

Holger Flatt, Ingo Schmadecke, Michael Kärgel, Holger Blume, Peter Pirsch: Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. ICSAMOS 2009: 125-132

Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch: Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams. SoCC 2009: 427-431

Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch: A parallel hardware architecture for connected component labeling based on fast label merging. ASAP 2008: 144-149

Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch: On the Benefit of Caching Traffic Flow Data in the Link Buffer. SAMOS 2008: 2-11

Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch: Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ARCS 2007: 254-267

Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch: RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. DSD 2007: 215-221

Norman Nolte, Winfried Gehrke, Frank Wiczinowski, Peter Pirsch: Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression. ICME 2007: 1187-1190

Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch: Design Space Exploration of Media Processors: A Parameterized Scheduler. ICSAMOS 2007: 41-49

Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch: A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. SAMOS 2007: 241-250

Guillermo Payá Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch: ChipDesign: from theory to real world. WCAE 2007: 58-64

Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch: HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. VLSI Signal Processing 41(1): 9-20 (2005)

Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch: A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. VLSI Signal Processing 41(2): 139-151 (2005)

Matthias Winter, Peter Pirsch: Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration. GI Jahrestagung (1) 2005: 458

Stefan Langemeyer, Christian Simon-Klar, Norman Nolte, Peter Pirsch: Architecture of a flexible on-board real-time SAR-processor. IGARSS 2005: 1746-1749

Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch: RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. SAMOS 2005: 32-40

Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch: HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Computer Architecture News 32(3): 55-61 (2004)

Mladen Berekovic, Sören Moch, Peter Pirsch: A scalable, clustered SMT processor for digital signal processing. SIGARCH Computer Architecture News 32(3): 62-69 (2004)

Carsten Reuter, Javier Martín-Langerwerf, Hans-Joachim Stolberg, Peter Pirsch: Performance Estimation of Streaming Media Applications for Reconfigurable Platforms. SAMOS 2004: 69-77

Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE 2003: 20008-20013

Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch: HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) 2003: 101-104

Jörn Jachalsky, Martin Wahler, Peter Pirsch, S. Capperon, Winfried Gehrke, W. M. Kruijtzer, Antonio Núñez: A core for ambient and mobile intelligent imaging applications. ICME 2003: 1-4

Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC 2003: 155-160

Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch: Multicore system-on-chip architecture for MPEG-4 streaming video. IEEE Trans. Circuits Syst. Video Techn. 12(8): 688-699 (2002)

Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo: Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. VLSI Signal Processing 31(2): 157-171 (2002)

Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch: HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. ICASSP 2002: 3112-3115

Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch: A platform-independent methodology for performance estimation of streaming media applications. ICME (2) 2002: 105-108

Javier Martín-Langerwerf, Carsten Reuter, Holger Kropp, Peter Pirsch: Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. IEEE International Workshop on Rapid System Prototyping 2002: 60-65

Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg: Processor Architectures for Multimedia Applications. Embedded Processor Design Challenges 2002: 188-206

Xun Mao, Wei Wang, Huimin Gong, Yan L. He, Jian Lou, Lu Yu, Qingdong Yao, Peter Pirsch: Highly efficient simulation environment for HDTV video decoder in VLSI design. VCIP 2002: 1006-1014

Peter Pirsch, Carsten Reuter, Jens Peter Wittenburg, Mark Bernd Kulaczewski, Hans-Joachim Stolberg: Architecture Concepts for Multimedia Signal Processing. VLSI Signal Processing 29(3): 157-165 (2001)

Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge: Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. ICME 2001

Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch: CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72

Carsten Reuter, Holger Kropp, Peter Pirsch: Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes). it+ti - Informationstechnik und Technische Informatik 42(3): 5-9 (2000)

Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo: Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP 2000: 15-24

Klaus Herrmann, Sören Moch, Jörg Hilgenstock, Peter Pirsch: Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. DFT 2000: 105-113

Dimitrios Soudris, Peter Pirsch, Erich Barke (Eds.): Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Lecture Notes in Computer Science 1918, Springer 2000, isbn 3-540-41068-6

Mohammad Ibrahim, Peter Pirsch, Johan McCanny: Guest Editors' Introduction. VLSI Signal Processing 22(1): 5-6 (1999)

Mladen Berekovic, Helge Kloos, Peter Pirsch: Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. VLSI Signal Processing 22(1): 31-43 (1999)

Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack: Instruction Set Extensions for MPEG-4 Video. VLSI Signal Processing 23(1): 27-49 (1999)

Hans-Joachim Stolberg, Martin Ohmacht, Peter Pirsch: Cellular Multiprocessor Arrays with Adaptive Resource Utilization. ACPC 1999: 480-489

Helge Kloos, Mladen Berekovic, Peter Pirsch: Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. ARCS 1999: 5-14

Jens Peter Wittenburg, Willm Hinrichs, Martin Ohmacht, Hanno Lieske, Helge Kloos, Peter Pirsch: HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. ARCS 1999: 15-21

Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch: An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. FPL 1999: 333-338

Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch: Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. Great Lakes Symposium on VLSI 1999: 42-45

Mladen Berekovic, K. Jacob, Peter Pirsch: Architecture of a hardware module for MPEG-4 shape decoding. ISCAS (1) 1999: 157-160

Peter Pirsch: Architectures for digital signal processing. Wiley 1998, isbn 978-0-471-97145-0, pp. I-XI, 1-419

Peter Pirsch, Hans-Joachim Stolberg: VLSI implementations of image and video multimedia processing systems. IEEE Trans. Circuits Syst. Video Techn. 8(7): 878-891 (1998)

Mladen Berekovic, Peter Pirsch, Johannes Kneip: An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. VLSI Signal Processing 20(1-2): 163-180 (1998)

Mladen Berekovic, Peter Pirsch: An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. Computer Graphics International 1998: 411-

Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch: A Video Signal Processor for MIMD Multiprocessing. DAC 1998: 50-55

Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch: Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC 1998: 56-61

Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch: A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. FPL 1998: 441-445

Holger Kropp, Carsten Reuter, Peter Pirsch: The Video and Image Processing Emulation System VIPES. International Workshop on Rapid System Prototyping 1998: 170-175

Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch: An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. VLSI Signal Processing 16(1): 31-40 (1997)

Carsten Reuter, Markus Schwiegershausen, Peter Pirsch: Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. ASAP 1997: 294-303

Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch: Implementation of pipelined multipliers on Xilinx FPGAs. FPL 1997: 51-60

Peter Pirsch: Architekturen der digitalen Signalverarbeitung. Informationstechnik, Teubner 1996, isbn 978-3-519-06157-1, pp. I-IX, 1-368

Johannes Kneip, Martin Ohmacht, Karsten Rönner, Peter Pirsch: Architecture and C++-programming environment of a highly parallel image signal processor. Microprocessing and Microprogramming 41(5-6): 391-408 (1995)

Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner: The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. VLSI Signal Processing 11(1-2): 51-74 (1995)

Markus Schwiegershausen, Peter Pirsch: A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. EURO-DAC 1995: 8-13

Peter Pirsch, Johannes Kneip, Karsten Rönner: Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. ISCAS 1995: 562-565

Marco Winzker, Peter Pirsch, Jochen Reimers: Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. ISCAS 1995: 609-612

Markus Schwiegershausen, Peter Pirsch: A system level design methodology for the optimization of heterogeneous multiprocessors. ISSS 1995: 162-169

Hans Georg Musmann, Peter Pirsch: Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite Broadcasting. European Transactions on Telecommunications 4(1): 11-21 (1993)

V. Hecht, Karsten Rönner, Peter Pirsch: A defect-tolerant systolic array implementation for real time image processing. VLSI Signal Processing 5(1): 37-47 (1993)

Klaus Gaedke, Hartwig Jeschke, Peter Pirsch: A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications. VLSI Signal Processing 5(2-3): 159-169 (1993)

Klaus Gaedke, Jens Franzen, Peter Pirsch: A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic. ISCAS 1993: 1583-1586

Peter Pirsch, Winfried Gehrke, R. Hoffer: A Hierarchical Multiprocessor Achitecture for Video Coding Applications. ISCAS 1993: 1750-1753

J. Schönfeld, Peter Pirsch: Single board image processing unit for vehicle guidance. VLSI 1993: 151-160

Hartwig Jeschke, Klaus Gaedke, Peter Pirsch: Multiprocessor performance for real-time processing of video coding applications. IEEE Trans. Circuits Syst. Video Techn. 2(2): 221-230 (1992)

Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch: Synthesis of intermediate memories for the data supply to processor arrays. Algorithms and Parallel VLSI Architectures 1991: 365-370

Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch: Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. VLSI 1991: 297-306

P. Drews, Peter Pirsch, K. Schaper: Circuit Technique for VLSI Design of a Video Codec. ICC (1) 1984: 250-255

Peter Pirsch, Arun N. Netravali: Transmission of gray level images by multilevel dither techniques. Computers & Graphics 7(1): 31-44 (1983)