Carl Pixley

Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley: Solver technology for system-level to RTL equivalence checking. DATE 2009: 196-201

Carl Pixley: Practical Considerations Concerning HL-to -RT Equivalence Checking. Haifa Verification Conference 2008: 6

Alfred Kölbl, Jerry R. Burch, Carl Pixley: Memory Modeling in ESL-RTL Equivalence Checking. DAC 2007: 205-209

In-Ho Moon, Per Bjesse, Carl Pixley: A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. DATE 2007: 1170-1175

Jun Yuan, Carl Pixley, Adnan Aziz: Constraint-based verification. Springer 2006, isbn 978-0-387-25947-5, pp. I-XII, 1-253

Sandeep K. Shukla, Carl Pixley, Gary Smith: Guest Editors' Introduction: The True State of the Art of ESL Design. IEEE Design & Test of Computers 23(5): 335-337 (2006)

In-Ho Moon, Per Bjesse, Carl Pixley: Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. HLDVT 2006: 170-175

Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley: Panel: Assertion-Based Verification -What's the Big Deal? HLDVT 2006: 183

Alfred Kölbl, Carl Pixley: Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. International Journal of Parallel Programming 33(6): 645-666 (2005)

Carl Pixley, Sharad Malik: Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Design & Test of Computers 21(6): 461-463 (2004)

Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin: Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 412-420 (2004)

In-Ho Moon, Carl Pixley: Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. FMCAD 2004: 144-158

Carl Pixley, D. Meyers, S. McMaster, A. Chittor: Designers want proofs - but show me the money. MEMOCODE 2004: 153-154

Carl Pixley, Juan Antonio Carballo: Panel Summaries. IEEE Design & Test of Computers 20(4): 86-88 (2003)

Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton: Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003)

Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Constraint synthesis for environment modeling in functional verification. DAC 2003: 296-299

Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi: Formal verification - prove it or pitch it. DAC 2003: 710-711

Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin: A Framework for Constrained Functional Verification. ICCAD 2003: 142-145

In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley: Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD 2002: 52-69

Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD 2002: 123-127

Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Simplifying Constraint Solving in Random Simulation Generation. IWLS 2002: 185-190

Carl Pixley: Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Design & Test of Computers 18(4): 4-5 (2001)

Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Theory of safe replacements for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001)

Shuvendu Lahiri, Carl Pixley, Ken Albin: Experience with term level modeling and verification of the M*CORE ^TM microprocessor core. HLDVT 2001: 109-114

Noel R. Strader, Gérard Memmi, Carl Pixley: Application of Formal Verification to Design Creation and Implementation. ISQED 2001: 11

Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho: An Efficient Logic Equivalence Checker for Industrial Circuits. J. Electronic Testing 16(1-2): 91-106 (2000)

Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz: Automatic Vector Generation Using Constraints and Biasing. J. Electronic Testing 16(1-2): 107-120 (2000)

Carl Pixley, Vigyan Singhal: Model Checking: A Hardware Design Perspective. STTT 2(3): 288-306 (1999)

Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz: Modeling design constraints and biasing in simulation using BDDs. ICCAD 1999: 584-590

Carl Pixley, Kurt Shultz, Jun Yuan: Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. PDPTA 1999: 1061-1068

Jainendra Kumar, Carl Pixley: Logic and Functional Verification in a Commercial Semiconductor Environment. ACSD 1998: 8-15

Matt Kaufmann, Andrew Martin, Carl Pixley: Design Constraints in Symbolic Model Checking. CAV 1998: 477-487

In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley: Approximate reachability don't cares for CTL model checking. ICCAD 1998: 351-358

Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley: Formal Verification of FIRE: A Case Study. DAC 1997: 173-177

Matt Kaufmann, Carl Pixley: Intertwined Development and Formal Verification of a 60x Bus Model. ICCD 1997: 25-30

Carl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen: Commercial Design Verification: Methodology and Tools. ITC 1996: 839-848

Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton: The Validity of Retiming Sequential Circuits. DAC 1995: 316-321

Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59

Vigyan Singhal, Robert K. Brayton, Carl Pixley: Power-Up Delay for Retiming Digital Circuits. ISCAS 1995: 566-569

Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel: Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1024-1034 (1994)

Vigyan Singhal, Carl Pixley: The Verifiacation Problem for Safe Replaceability. CAV 1994: 311-323

Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton: Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449

Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley: Synchronizing sequences and symbolic traversal techniques in test generation. J. Electronic Testing 4(1): 19-31 (1993)

June-Kyung Rho, Fabio Somenzi, Carl Pixley: Minimum Length Synchronizing Sequences of Finite State Machine. DAC 1993: 463-468

Carl Pixley: A theory and implementation of sequential hardware equivalence. IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1469-1478 (1992)

Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel: Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC 1992: 620-623

Carl Pixley, Gary Beihl: Calculating Resetability and Reset Sequences. ICCAD 1991: 376-379

Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes: Automatic Derivation of FSM Specification to Implementation Encoding. ICCD 1991: 245-249

Carl Pixley: Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. CAV 1990: 54-64

Carl Pixley: An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. Distributed Computing 3(1): 41-50 (1988)