Geert Van der Plas

Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne: Design issues in heterogeneous 3D/2.5D integration. ASP-DAC 2013: 403-410

Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert: RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. J. Solid-State Circuits 47(4): 990-1002 (2012)

Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas: A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. on Circuits and Systems 59-I(1): 80-92 (2012)

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal: Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. J. Solid-State Circuits 46(1): 293-307 (2011)

Herman Oprins, A. Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, E. Cheng: Fine grain thermal modeling and experimental validation of 3D-ICs. Microelectronics Journal 42(4): 572-578 (2011)

Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne: In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6

Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, W. Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte: Analysis of microbump induced stress effects in 3D stacked IC technologies. 3DIC 2011: 1-5

Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas: DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. CICC 2011: 1-4

Eric Beyne, Pol Marchal, Geert Van der Plas: 3D heterogeneous system integration: application driver for 3D technology development. DAC 2011: 213

Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas: An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. DATE 2011: 505-506

Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx: A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. J. Solid-State Circuits 45(6): 1159-1171 (2010)

Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert: Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. J. Solid-State Circuits 45(6): 1198-1208 (2010)

Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas: A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. J. Solid-State Circuits 45(10): 2080-2090 (2010)

Stephane Bronckers, Geert Van der Plas, Gerd Vandersteen, Yves Rolain: Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. IEEE T. Instrumentation and Measurement 59(6): 1727-1733 (2010)

Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal: Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC 2010: 1-4

Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal: 3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217

Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne: Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149

Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas: A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC 2010: 296-297

Sergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci: Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. IEICE Transactions 92-C(6): 843-851 (2009)

Guy Torfs, Zhisheng Li, Johan Bauwelinck, Xin Yin, Jan Vandewege, Geert Van der Plas: A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs. IEICE Transactions 92-C(10): 1328-1330 (2009)

Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain: A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1613-1626 (2009)

Stephane Bronckers, Gerd Vandersteen, Ludwig De Locht, Michael Libois, Geert Van der Plas, Yves Rolain: Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO. IEEE T. Instrumentation and Measurement 58(8): 2706-2713 (2009)

Panagiotis Asimakopoulos, Geert Van der Plas, Alexandre Yakovlev, Paul Marchal: Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. 3DIC 2009: 1-5

Dragomir Milojevic, Trevor Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal: Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. 3DIC 2009: 1-6

Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas: A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. ISSCC 2009: 176-177

Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, Geert Van der Plas: Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. IEEE Trans. on Circuits and Systems 55-I(6): 1441-1454 (2008)

Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas: Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. DATE 2008: 1390-1393

Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain: Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. DATE 2007: 1520-1525

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941

Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. CoRR abs/0710.4723 (2007)

Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke: Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wireless Comm. and Networking 2006 (2006)

Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006)

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. VLSI Syst. 14(1): 23-33 (2006)

Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni: A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC 2006: 873-878

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005)

Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275

Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93

Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen: A layout synthesis methodology for array-type analog blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 645-661 (2002)

Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: CYCLONE: automated design and layout of RF LC-oscillators. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1161-1170 (2002)

Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts: AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1037-1058 (2001)

Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: A Layout-Aware Synthesis Methodology for RF Circuits. ICCAD 2001: 358-

Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: CYCLONE: automated design and layout of RF LC-oscillators. DAC 2000: 11-14

Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen: Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. DAC 2000: 452-457

Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen: Automated test pattern generation for analog integrated circuits. VTS 1997: 296-301