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Ilia Polian
2010 – today
- 2013
[c68]Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker: Provably optimal test cube generation using quantified boolean formula solving. ASP-DAC 2013: 533-539- [c67]Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker: Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. DATE 2013: 448-453
- 2012
- [c66]Alexandru Paler, Ilia Polian, John P. Hayes: Detection and diagnosis of faulty quantum circuits. ASP-DAC 2012: 181-186
- [c65]Ilia Polian: Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Asian Test Symposium 2012: 49
- [c64]Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich: Variation-Aware Fault Grading. Asian Test Symposium 2012: 344-349
- [c63]Philipp Jovanovic, Martin Kreuzer, Ilia Polian: A Fault Attack on the LED Block Cipher. COSADE 2012: 120-134
- [c62]Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian: On the optimality of K longest path generation algorithm under memory constraints. DATE 2012: 418-423
- [c61]Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker: #SAT-based vulnerability analysis of security components - A case study. DFT 2012: 49-54
- [c60]Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker: Multi-conditional SAT-ATPG for power-droop testing. European Test Symposium 2012: 1-6
- [c59]Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian: On the quality of test vectors for post-silicon characterization. European Test Symposium 2012: 1-6
- [c58]Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker: Small-delay-fault ATPG with waveform accuracy. ICCAD 2012: 30-36
- [c57]Victor Tomashevich, Sudarshan Srinivasan, Fabian Foerg, Ilia Polian: Cross-level protection of circuits against faults and malicious attacks. IOLTS 2012: 150-155
- [c56]Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8
- [c55]Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker: SAT-ATPG using preferences for improved detection of complex defect mechanisms. VTS 2012: 170-175
- [i3]Philipp Jovanovic, Martin Kreuzer, Ilia Polian: An Algebraic Fault Attack on the LED Block Cipher. IACR Cryptology ePrint Archive 2012: 400 (2012)
- 2011
- [j20]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-aware fault modeling. SCIENCE CHINA Information Sciences 54(9): 1813-1826 (2011)
- [j19]Ilia Polian, John P. Hayes: Selective Hardening: Toward Cost-Effective Error Tolerance. IEEE Design & Test of Computers 28(3): 54-63 (2011)
- [j18]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker: Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Sec. Comput. 8(4): 537-547 (2011)
- [c54]Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker: Efficient SAT-Based Search for Longest Sensitisable Paths. Asian Test Symposium 2011: 108-113
- [c53]Philipp Klaus Krause, Ilia Polian: Adaptive voltage over-scaling for resilient applications. DATE 2011: 944-949
- [c52]Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker: SAT-based analysis of sensitisable paths. DDECS 2011: 93-98
- [c51]Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes: Tomographic Testing and Validation of Probabilistic Circuits. European Test Symposium 2011: 63-68
- [c50]Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell: Towards Variation-Aware Test Methods. European Test Symposium 2011: 219-225
- [c49]Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker: Estimation of component criticality in early design steps. IOLTS 2011: 104-110
- [c48]Matthias Sauer, Victor Tomashevich, J. Muller, Matthew D. T. Lewis, A. Spilla, Ilia Polian, Bernd Becker, W. Burgard: An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. IOLTS 2011: 182-185
- 2010
- [j17]Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. International Journal of Parallel Programming 38(3-4): 185-202 (2010)
- [j16]Ilia Polian, Bernd Becker: Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). it - Information Technology 52(4): 189-194 (2010)
- [j15]Ilia Polian: Power Supply Noise: Causes, Effects, and Testing. J. Low Power Electronics 6(2): 326-338 (2010)
- [c47]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-Aware Fault Modeling. Asian Test Symposium 2010: 87-93
- [c46]
- [c45]Ilia Polian: Special session 4B: Panel low-power test and noise-aware test: Foes or friends? VTS 2010: 130
2000 – 2009
- 2009
- [j14]Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian: SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009)
- [c44]Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190
- [c43]Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng: Analysis and optimization of fault-tolerant embedded systems with hardened processors. DATE 2009: 682-687
- [c42]Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker: Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI 2009: 63-68
- [c41]Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker: ATPG-based grading of strong fault-secureness. IOLTS 2009: 269-274
- [c40]Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232
- [c39]Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker: An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26
- 2008
- [j13]Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
- [c38]Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker: Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633
- [c37]Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen: Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266
- [c36]Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker: On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253
- [c35]
- [c34]Damian Nowroth, Ilia Polian, Bernd Becker: A study of cognitive resilience in a JPEG compressor. DSN 2008: 32-41
- [c33]Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker: A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. European Test Symposium 2008: 113-118
- [c32]Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker: Selective Hardening in Early Design Steps. European Test Symposium 2008: 185-190
- [c31]Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI 2008: 257-262
- [c30]Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10
- [c29]Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186
- 2007
- [j12]Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. IEEE Design & Test of Computers 24(3): 276-284 (2007)
- [j11]Ilia Polian, Hideo Fujiwara: Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J. Electronic Testing 23(5): 445-455 (2007)
- [c28]Ilia Polian, Damian Nowroth, Bernd Becker: Identification of Critical Errors in Imaging Applications. IOLTS 2007: 201-202
- [c27]John P. Hayes, Ilia Polian, Bernd Becker: An Analysis Framework for Transient-Error Tolerance. VTS 2007: 249-255
- [i2]Ilia Polian, Alejandro Czutro, Bernd Becker: Evolutionary Optimization in Code-Based Test Compression. CoRR abs/0710.4670 (2007)
- [i1]Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, O. Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther: Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. CoRR abs/0711.3289 (2007)
- 2006
- [j10]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006)
- [j9]Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich: DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it - Information Technology 48(5): 304- (2006)
- [j8]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006)
- [j7]Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. VLSI Syst. 14(2): 193-202 (2006)
- [c26]Ilia Polian, Hideo Fujiwara: Functional constraints vs. test compression in scan-based delay testing. DATE 2006: 1039-1044
- [c25]Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm: Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. DDECS 2006: 15-20
- [c24]Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara: Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279
- [c23]
- [c22]Sandip Kundu, Ilia Polian: An Improved Technique for Reducing False Alarms Due to Soft Errors. IOLTS 2006: 105-110
- [c21]Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Ilia Polian, Jochen Eisinger, Bernd Becker: A Definition and Classification of Timing Anomalies. WCET 2006
- 2005
- [j6]Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005)
- [j5]Ilia Polian: Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). it - Information Technology 47(3): 172-174 (2005)
- [c20]Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271
- [c19]Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes: A Family of Logical Fault Models for Reversible Circuits. Asian Test Symposium 2005: 422-427
- [c18]Ilia Polian, Alejandro Czutro, Bernd Becker: Evolutionary Optimization in Code-Based Test Compression. DATE 2005: 1124-1129
- [c17]Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker: Transient fault characterization in dynamic noisy environments. ITC 2005: 10
- [c16]Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348
- 2004
- [j4]Ilia Polian, Bernd Becker: Scalable Delay Fault BIST for Use with Low-Cost ATE. J. Electronic Testing 20(2): 181-197 (2004)
- [c15]John P. Hayes, Ilia Polian, Bernd Becker: Testing for Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2004: 100-105
- [c14]Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker: X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451
- [c13]Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer: Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. MBMV 2004: 65-75
- [c12]Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178
- 2003
- [j3]Ilia Polian, Bernd Becker: Multiple Scan Chain Design for Two-Pattern Testing. J. Electronic Testing 19(1): 37-48 (2003)
- [j2]Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker: Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. J. Electronic Testing 19(4): 387-395 (2003)
- [j1]Ilia Polian, Wolfgang Günther, Bernd Becker: Pattern-based verification of connections to intellectual property cores. Integration 35(1): 25-44 (2003)
- [c11]Ilia Polian, Bernd Becker, Sudhakar M. Reddy: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE 2003: 11184-11185
- [c10]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059
- [c9]
- [c8]
- 2002
- [c7]Ilia Polian, Irith Pomeranz, Bernd Becker: Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Asian Test Symposium 2002: 2-14
- [c6]
- [c5]Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker: Sequential n -Detection Criteria: Keep It Simple. IOLTW 2002: 189
- [c4]Ilia Polian, Piet Engelke, Bernd Becker: Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. ISMVL 2002: 216-
- 2001
- [c3]Ilia Polian, Wolfgang Günther, Bernd Becker: Efficient Pattern-Based Verification of Connections to IP Cores . Asian Test Symposium 2001: 443-448
- [c2]Ilia Polian, Wolfgang Günther, Bernd Becker: Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. MBMV (1) 2001: 111-120
- [c1]
Coauthor Index
[c68] [c67] [c64] [c62] [c61] [c60] [c59] [c58] [c56] [c55] [j20] [j18] [c54] [c52] [c50] [c49] [c48] [j17] [j16] [c47] [j14] [c44] [c42] [c41] [c40] [c39] [j13] [c38] [c37] [c36] [c34] [c33] [c32] [c31] [c30] [c29] [j12] [c28] [c27] [i2] [i1] [j10] [j9] [j8] [j7] [c25] [c24] [c23] [c21] [j6] [c20] [c19] [c18] [c17] [c16] [j4] [c15] [c14] [c13] [c12] [j3] [j2] [j1] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-05-25 21:23 CEST by the dblp team