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 | 2012 | |
|---|---|---|
| c8 |      | Julian J. H. Pontes, Ney Calazans, Pascal Vivet: Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC 2012: 142-149 |
| c7 | | Julian J. H. Pontes, Ney Calazans, Pascal Vivet: An accurate Single Event Effect digital design flow for reliable system level design. DATE 2012: 224-229 |
| 2011 | ||
| c6 | | Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans: Adapting a C-element design flow for low power. ICECS 2011: 45-48 |
| c5 | | Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans: A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104 |
| 2010 | ||
| c4 | | Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 |
| c3 | | Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498 |
| 2008 | ||
| c2 | | Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans: Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352 |
| 2007 | ||
| c1 | | Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans: SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546 |
| 1 | Ney Laert Vilar Calazans (Ney Calazans) | |
| 2 | Ewerson Carvalho (Ewerson Luiz de Souza Carvalho) | |
| 3 | Fernando Gehm Moraes (Fernando Moraes) | |
| 4 | Matheus T. Moreira | |
| 5 | Bruno Cruz de Oliveira | |
| 6 | Rafael Soares (Rafael Iankowski Soares) | |
| 7 | Pascal Vivet |
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