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 | 2011 | |
|---|---|---|
| c15 |      | Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David Brooks: Achieving uniform performance and maximizing throughput in the presence of heterogeneity. HPCA 2011: 3-14 |
| 2009 | ||
| c14 | | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi: CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA 2009: 289-300 |
| c13 | | Michael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee: Architectural core salvaging in a multi-core processor for hard-error tolerance. ISCA 2009: 93-104 |
| 2007 | ||
| c12 | | Michael D. Powell, T. N. Vijaykumar: Resource area dilation to reduce power density in throughput servers. ISLPED 2007: 268-273 |
| 2005 | ||
| c11 | | Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar: Optimizing Replication, Communication, and Capacity Allocation in CMPs. ISCA 2005: 357-368 |
| c10 | | Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar: Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. MICRO 2005: 294-304 |
| 2004 | ||
| c9 | | Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar: Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. ASPLOS 2004: 260-270 |
| c8 | | Michael D. Powell, T. N. Vijaykumar: Exploiting Resonant Behavior to Reduce Inductive Noise. ISCA 2004: 288-301 |
| 2003 | ||
| c7 | | Michael D. Powell, T. N. Vijaykumar: Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. ISCA 2003: 72-83 |
| c6 | | Michael D. Powell, T. N. Vijaykumar: Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. ISLPED 2003: 223-228 |
| c5 | | Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar: Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. MICRO 2003: 55-66 |
| 2002 | ||
| c4 | | Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar: Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. HPCA 2002: 151-161 |
| c3 | | Il Park, Michael D. Powell, T. N. Vijaykumar: Reducing register ports for higher speed and lower energy. MICRO 2002: 171-182 |
| 2001 | ||
| j1 | | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. VLSI Syst. 9(1): 77-89 (2001) |
| c2 | | Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-157 |
| c1 | | Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy: Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65 |
Colors in the list of coauthors
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