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Dhiraj K. Pradhan
2010 – today
- 2013
[c126]Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan: A fast and Effective DFT for test and diagnosis of power switches in SoCs. DATE 2013: 1089-1092- 2012
- [j86]Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan: Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integration 45(1): 33-45 (2012)
- [j85]Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. J. Low Power Electronics 8(3): 270-282 (2012)
- [c125]Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: STEP: a unified design methodology for secure test and IP core protection. ACM Great Lakes Symposium on VLSI 2012: 333-338
- [c124]Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. ISVLSI 2012: 189-194
- [c123]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269
- 2011
- [j84]Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan: Fault Tolerant Single Error Correction Encoders. J. Electronic Testing 27(2): 215-218 (2011)
- [j83]Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan: Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks. IJSNet 10(3): 160-175 (2011)
- [j82]Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski: A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electronics 7(4): 471-481 (2011)
- [j81]Costas Argyrides, Raul Chipana, Fabian Vargas, Dhiraj K. Pradhan: Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction. IEEE Transactions on Reliability 60(3): 528-537 (2011)
- [j80]Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak: Matrix Codes for Reliable and Cost Efficient Memory Chips. IEEE Trans. VLSI Syst. 19(3): 420-428 (2011)
- [j79]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. VLSI Syst. 19(8): 1469-1480 (2011)
- [j78]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty: A Routing-Aware ILS Design Technique. IEEE Trans. VLSI Syst. 19(12): 2335-2338 (2011)
- [c122]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. ECCTD 2011: 600-603
- [c121]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty: BCH code based multiple bit error correction in finite field multiplier circuits. ISQED 2011: 615-620
- [c120]S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski: Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309
- 2010
- [j77]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Comput. J. 53(5): 581-591 (2010)
- [j76]Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan: A Galois field-based logic synthesis with testability. IET Computers & Digital Techniques 4(4): 263-273 (2010)
- [j75]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. IET Computers & Digital Techniques 4(5): 428-437 (2010)
- [j74]Taskin Koçak, Dhiraj K. Pradhan: Introduction to design techniques for energy harvesting. JETC 6(2) (2010)
- [j73]Saraju P. Mohanty, Dhiraj K. Pradhan: ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management. JETC 6(2) (2010)
- [j72]Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos: DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. J. Low Power Electronics 6(3): 390-400 (2010)
- [j71]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Test Generation in Systolic Architecture for Multiplication Over GF(2 m). IEEE Trans. VLSI Syst. 18(9): 1366-1371 (2010)
- [c119]Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan: Improving reliability for bit parallel finite field multipliers using Decimal Hamming. EWDTS 2010: 69-72
- [c118]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan: A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ACM Great Lakes Symposium on VLSI 2010: 323-328
- [c117]Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan: A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ISQED 2010: 131-138
- [c116]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan: P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. ISQED 2010: 176-183
- [c115]Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan: On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218
- [c114]Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Layout-aware Illinois Scan design for high fault coverage coverage. ISQED 2010: 683-688
- [c113]Costas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan: Improved Yield in Nanotechnology Circuits Using Non-square Meshes. ISVLSI 2010: 410-415
- [c112]Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan: Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. PerCom Workshops 2010: 456-461
- [c111]Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir: On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291
- [c110]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan: A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. VLSI Design 2010: 45-50
2000 – 2009
- 2009
- [j70]Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single error correctable bit parallel multipliers over GF(2m). IET Computers & Digital Techniques 3(3): 281-288 (2009)
- [j69]Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan: An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a. Quantum Information & Computation 9(7): 610-621 (2009)
- [c109]Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew: Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922
- [c108]Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro: A fast error correction technique for matrix multiplication algorithms. IOLTS 2009: 133-137
- [c107]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211
- [c106]Costas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan: Increasing memory yield in future technologies through innovative design. ISQED 2009: 622-626
- [c105]Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro: Reliability aware yield improvement technique for nanotechnology based circuits. SBCCI 2009
- [c104]Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312
- 2008
- [j68]Hongwei Zhu, Ilie I. Luican, Florin Balasa, Dhiraj K. Pradhan: Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems. IEICE Transactions 91-A(12): 3559-3567 (2008)
- [j67]Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan: Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis. IET Computers & Digital Techniques 2(2): 118-131 (2008)
- [j66]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008)
- [j65]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008)
- [j64]Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan: Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1689-1692 (2008)
- [j63]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
- [c103]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373
- [c102]Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. IOLTS 2008: 16-21
- [c101]Costas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan: Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IOLTS 2008: 155-160
- [c100]Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan: Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS 2008: 188-189
- [c99]Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan: Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687
- [c98]Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337
- [c97]Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan: Area Reliability Trade-Off in Improved Reed Muller Coding. SAMOS 2008: 116-125
- [c96]Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan: Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190
- [c95]Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246
- [c94]Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254
- [c93]Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan: On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. TQC 2008: 96-104
- [c92]Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38
- [c91]Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan: Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459
- [c90]Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634
- [c89]Carlos Arthur Lang Lisbôa, Costas Argyrides, Dhiraj K. Pradhan, Luigi Carro: Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. VTS 2008: 363-370
- [p1]Bharat Joshi, Dhiraj K. Pradhan, Jack Stiffler: Fault-Tolerant Computing. Wiley Encyclopedia of Computer Science and Engineering 2008
- 2007
- [j62]Abusaleh M. Jabir, Dhiraj K. Pradhan: A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. IEEE Trans. Computers 56(8): 1119-1132 (2007)
- [j61]Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh: A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. IEEE Trans. Computers 56(8): 1133-1145 (2007)
- [c88]Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan: Single Event Upset Detection and Correction. ICIT 2007: 13-18
- [c87]Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan: Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT 2007: 340-348
- [c86]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Reliable network-on-chip based on generalized de Bruijn graph. HLDVT 2007: 3-10
- [c85]
- [c84]Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208
- [c83]Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan: Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. IPDPS 2007: 1-6
- [c82]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144
- [c81]Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan: Multiple Upsets Tolerance in SRAM Memory. ISCAS 2007: 365-368
- [c80]R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005
- [c79]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678
- [c78]Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan: CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. ISCAS 2007: 3696-3699
- [c77]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385
- [c76]S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan: Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. ISQED 2007: 807-813
- [c75]Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan: A soft error robust and power aware memory design. SBCCI 2007: 300-305
- [c74]Costas Argyrides, Dhiraj K. Pradhan: Improved decoding algorithm for high reliable reed muller coding. SoCC 2007: 95-98
- [c73]Costas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan: High defect tolerant low cost memory chips. SoCC 2007: 119-122
- [c72]Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan: A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. SoCC 2007: 309-312
- [c71]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484
- [c70]Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430
- 2006
- [c69]Chunsheng Liu, Zach Link, Dhiraj K. Pradhan: Reuse-based test access and integrated test scheduling for network-on-chip. DATE 2006: 303-308
- [c68]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54
- [c67]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: An efficient technique for synthesis and optimization of polynomials in GF(2m). ICCAD 2006: 151-157
- [c66]Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan: Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51
- 2005
- [j60]Dhiraj K. Pradhan, Chunsheng Liu: EBIST: a novel test generator with built-in fault detection capability. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1457-1466 (2005)
- [c65]Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir: GASIM: a fast Galois field based simulator for functional model. HLDVT 2005: 135-142
- [c64]Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir: A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. IOLTS 2005: 221-226
- [c63]S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan: Comparative study of CA with phase shifters and GLFSRs. ITC 2005: 10
- [c62]Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea: Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design 2005: 14
- 2004
- [j59]Subhasis Bhattacharjee, Dhiraj K. Pradhan: LPRAM: a novel low-power high-performance RAM design with testability and scalability. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 637-651 (2004)
- [c61]Subhasis Bhattacharjee, Dhiraj K. Pradhan: LPRAM: a low power DRAM with testability. ASP-DAC 2004: 390-393
- [c60]Abusaleh M. Jabir, Dhiraj K. Pradhan: MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. DATE 2004: 1388-1389
- [c59]T. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: MODD for CF: a representation for fast evaluation of multiple-output functions. HLDVT 2004: 61-66
- [c58]Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan: Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. ITC 2004: 1369-1378
- [c57]Sathiamoorthy Subbarayan, Dhiraj K. Pradhan: NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances. SAT 2004
- [c56]Sathiamoorthy Subbarayan, Dhiraj K. Pradhan: NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances. SAT (Selected Papers 2004: 276-291
- 2003
- [j58]Mitrajit Chatterjee, Dhiraj K. Pradhan: A BIST Pattern Generator Design for Near-Perfect Fault Coverage. IEEE Trans. Computers 52(12): 1543-1558 (2003)
- [c55]Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty: EBIST: A Novel Test Generator with Built-In Fault Detection Capability. DATE 2003: 10224-10229
- [c54]Dhiraj K. Pradhan: Logic transformation and coding theory-based frameworks for Boolean satisfiability. HLDVT 2003: 57-62
- [c53]Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski: Mathematical framework for representing discrete functions as word-level polynomials. HLDVT 2003: 135-139
- [c52]Elango Ganesan, Dhiraj K. Pradhan: Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. ISCAS (3) 2003: 870-873
- 2001
- [c51]Dhiraj K. Pradhan: Logic Insertion to Speed-Up Logic Verification: A Recent Development. IOLTW 2001: 61-64
- [c50]Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma: ATPG for Design Errors-Is It Possible? VTS 2001: 283-285
- 2000
- [j57]Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan: Buffer Assignment Algorithms on Data Driven ASICs. IEEE Trans. Computers 49(1): 16-32 (2000)
- [j56]Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan: VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000)
1990 – 1999
- 1999
- [j55]Dhiraj K. Pradhan, Mitrajit Chatterjee: GLFSR-a new test pattern generator for built-in-self-test. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 238-247 (1999)
- 1998
- [j54]Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998)
- [j53]Debendra Das Sharma, Dhiraj K. Pradhan: Job Scheduling in Mesh Multicomputers. IEEE Trans. Parallel Distrib. Syst. 9(1): 57-70 (1998)
- 1997
- [j52]P. Krishna, Nitin H. Vaidya, Mainak Chatterjee, Dhiraj K. Pradhan: A cluster-based approach for routing in dynamic networks. Computer Communication Review 27(2): 49-64 (1997)
- [j51]Dhiraj K. Pradhan, Nitin H. Vaidya: Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. IEEE Trans. Computers 46(3): 372-378 (1997)
- [c49]Bikram S. Bakshi, P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan: Improving Performance of TCP over Wireless Networks. ICDCS 1997: 0-
- 1996
- [j50]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan: Static and adaptive location management in mobile wireless networks. Computer Communications 19(4): 321-334 (1996)
- [j49]Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch: Modified tree structure for location management in mobile environments. Computer Communications 19(4): 335-345 (1996)
- [j48]Debendra Das Sharma, Dhiraj K. Pradhan: Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability. J. Parallel Distrib. Comput. 36(2): 106-118 (1996)
- [j47]Sandeep K. Gupta, Dhiraj K. Pradhan: Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996)
- [j46]Nicholas S. Bowen, Dhiraj K. Pradhan: The Effect of Program Behavior on Fault Observability. IEEE Trans. Computers 45(8): 868-880 (1996)
- [j45]Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy: A novel framework for logic verification in a synthesis environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996)
- [j44]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of initializable asynchronous circuits. IEEE Trans. VLSI Syst. 4(2): 254-263 (1996)
- [c48]Dhiraj K. Pradhan, P. Krishna, Nitin H. Vaidya: Recoverable Mobile Environment: Design and Trade-Off Analysis. FTCS 1996: 16-25
- [c47]Wanlin Cao, Dhiraj K. Pradhan: Sequential redundancy identification using recursive learning. ICCAD 1996: 56-62
- [c46]Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee: VERILAT: verification using logic augmentation and transformations. ICCAD 1996: 88-95
- [c45]Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz: Gate-level synthesis for low-power using new transformations. ISLPED 1996: 297-300
- [c44]Bikram S. Bakshi, P. Krishna, Dhiraj K. Pradhan, Nitin H. Vaidya: Providing Seamless Communication in Mobile Wireless Networks. LCN 1996: 535-543
- 1995
- [j43]Jeffrey A. Clark, Dhiraj K. Pradhan: Fault Injection: A Method for Validating Computer-System Dependability. IEEE Computer 28(6): 47-56 (1995)
- [j42]Nicholas S. Bowen, Dhiraj K. Pradhan: A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms. IEEE Trans. Computers 44(3): 408-418 (1995)
- [j41]Dhiraj K. Pradhan, Jayashree Saxena: A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1577-1586 (1995)
- [j40]Debendra Das Sharma, Dhiraj K. Pradhan: Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation. IEEE Trans. Parallel Distrib. Syst. 6(10): 1108-1122 (1995)
- [c43]Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. DAC 1995: 414-419
- [c42]Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325
- [c41]Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch: Modified Tree Structure for Location Management in Mobile Environments. INFOCOM 1995: 530-537
- [c40]P. Krishna, Mainak Chatterjee, Nitin H. Vaidya, Dhiraj K. Pradhan: A Cluster-based Approach for Routing in Ad-Hoc Networks. Symposium on Mobile and Location-Independent Computing 1995: 1-10
- [c39]Mitrajit Chatterjee, Dhiraj K. Pradhan: A novel pattern generator for near-perfect fault-coverage. VTS 1995: 417-425
- 1994
- [j39]Nitin H. Vaidya, Dhiraj K. Pradhan: Safe System Level Diagnosis. IEEE Trans. Computers 43(3): 367-370 (1994)
- [j38]Dhiraj K. Pradhan, Nitin H. Vaidya: Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture. IEEE Trans. Computers 43(10): 1163-1174 (1994)
- [j37]Wolfgang Kunz, Dhiraj K. Pradhan: Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1143-1158 (1994)
- [c38]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670
- [c37]Dhiraj K. Pradhan, Nitin H. Vaidya: Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. FTCS 1994: 186-195
- [c36]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452
- [c35]Debendra Das Sharma, G. D. Holland, Dhiraj K. Pradhan: Subcube Level Time-Sharing in Hypercube Multicomputers. ICPP 1994: 134-142
- [c34]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan: Recovery in Multicomputers with Finite Error Detection Latency. ICPP 1994: 206-210
- [c33]
- [c32]Barun K. Kar, Khadem M. Yusuf, Dhiraj K. Pradhan: Bit-Serial Generalized Median Filters. ISCAS 1994: 85-88
- [c31]Dhiraj K. Pradhan, Mitrajit Chatterjee: GLFSR - A New Test Pattern Generator for Built-In Self-Test. ITC 1994: 481-490
- [c30]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan: Location Management in Distributed Mobile Environments. PDIS 1994: 81-88
- [c29]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388
- [c28]Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan: Functional learning: a new approach to learning in digital circuits. VTS 1994: 122-127
- 1993
- [j36]Nicholas S. Bowen, Dhiraj K. Pradhan: Processor- and Memory-Based Checkpoint and Rollback Recovery. IEEE Computer 26(2): 22-31 (1993)
- [j35]Dhiraj K. Pradhan, Fred J. Meyer: Communication structures in fault-tolerant distributed systems. Networks 23(4): 379-389 (1993)
- [j34]Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan: Modeling Live and Dead Lines in Cache Memory Systems. IEEE Trans. Computers 42(1): 1-14 (1993)
- [j33]Nitin H. Vaidya, Dhiraj K. Pradhan: Fault-Tolerant Design Strategies for High Reliability and Safety. IEEE Trans. Computers 42(10): 1195-1206 (1993)
- [j32]Wolfgang Kunz, Dhiraj K. Pradhan: Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 684-694 (1993)
- [j31]Elango Ganesan, Dhiraj K. Pradhan: The Hyper-deBruijn Networks: Scalable Versatile Architecture. IEEE Trans. Parallel Distrib. Syst. 4(9): 962-978 (1993)
- [j30]Barun K. Kar, Dhiraj K. Pradhan: A new algorithm for order statistic and sorting. IEEE Transactions on Signal Processing 41(8): 2688-2694 (1993)
- [j29]D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan: Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. IEEE Trans. VLSI Syst. 1(4): 546-558 (1993)
- [c27]Dhiraj K. Pradhan, Debendra Das Sharma, Nitin H. Vaidya: Roll-Forward Checkpointing Schemes. Hardware and Software Architectures for Fault Tolerance 1993: 95-116
- [c26]Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee: Buffer assignment for data driven architectures. ICCAD 1993: 665-668
- [c25]Jayashree Saxena, Dhiraj K. Pradhan: Desgin for Testability of Asynchronous Sequential Circuits. ICCD 1993: 518-522
- [c24]Nitin H. Vaidya, Dhiraj K. Pradhan: Degradable Agreement in the Presence of Byzantine Faults. ICDCS 1993: 237-244
- [c23]Debendra Das Sharma, Dhiraj K. Pradhan: Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors. ICPP 1993: 118-127
- [c22]Elango Ganesan, Dhiraj K. Pradhan: Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks. IPPS 1993: 655-660
- [c21]Jayashree Saxena, Dhiraj K. Pradhan: A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. ITC 1993: 724-733
- [c20]Debendra Das Sharma, Dhiraj K. Pradhan: A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers. SPDP 1993: 682-689
- [c19]
- 1992
- [j28]Nicholas S. Bowen, Dhiraj K. Pradhan: Virtual Checkpoints: Architecture and Performance. IEEE Trans. Computers 41(5): 516-525 (1992)
- [j27]Nitin H. Vaidya, Dhiraj K. Pradhan: A new class of bit- and byte-error control codes. IEEE Transactions on Information Theory 38(5): 1617-1623 (1992)
- [c18]Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut: A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors. IPPS 1992: 43-46
- [c17]
- [c16]Wolfgang Kunz, Dhiraj K. Pradhan: Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. ITC 1992: 816-825
- [c15]Debendra Das Sharma, Dhiraj K. Pradhan: A Novel Approach for Subcube Allocation in Hypercube Multiprocessors. SPDP 1992: 336-345
- 1991
- [j26]Dhiraj K. Pradhan, Sandeep K. Gupta: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991)
- [j25]Fred J. Meyer, Dhiraj K. Pradhan: Consensus With Dual Failure Modes. IEEE Trans. Parallel Distrib. Syst. 2(2): 214-222 (1991)
- [c14]Nicholas S. Bowen, Dhiraj K. Pradhan: Program Fault Tolerance Based on Memory Access Behavior. FTCS 1991: 426-435
- [c13]Nitin H. Vaidya, Dhiraj K. Pradhan: System Level Diagnosis: Combining Detection and Location. FTCS 1991: 488-495
- [c12]
- [c11]Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan: Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839
- [c10]Nicholas S. Bowen, Dhiraj K. Pradhan: A virtual memory translation mechanism to support checkpoint and rollback recovery. SC 1991: 890-899
- [c9]Neeraj Suri, Avi Mendelson, Dhiraj K. Pradhan: BDG-torus union graph-an efficient algorithmically specializedparallel interconnect. SPDP 1991: 407-414
- 1990
- [j24]Eiji Fujiwara, Dhiraj K. Pradhan: Error-Control Coding in Computers. IEEE Computer 23(7): 63-72 (1990)
- [j23]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan: Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers 39(1): 63-71 (1990)
- [j22]Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky: Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990)
- [c8]Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy: Zero aliasing compression. FTCS 1990: 254-263
- [c7]Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan: Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. ICPP (1) 1990: 326-330
1980 – 1989
- 1989
- [j21]Fred J. Meyer, Dhiraj K. Pradhan: Dynamic Testing Strategy for Distributed Systems. IEEE Trans. Computers 38(3): 356-365 (1989)
- [j20]Fred J. Meyer, Dhiraj K. Pradhan: Modeling Defect Spatial Distribution. IEEE Trans. Computers 38(4): 538-546 (1989)
- [j19]Maheswara R. Samatham, Dhiraj K. Pradhan: The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI. IEEE Trans. Computers 38(4): 567-581 (1989)
- 1988
- [j18]Fred J. Meyer, Dhiraj K. Pradhan: Flip-Trees: Fault-Tolerant Graphs with Wide Containers. IEEE Trans. Computers 37(4): 472-478 (1988)
- [j17]Najmi T. Jarwala, Dhiraj K. Pradhan: TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's. IEEE Trans. Computers 37(10): 1235-1250 (1988)
- [c6]Dhiraj K. Pradhan, Nirmala R. Kamath: RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. ITC 1988: 263-278
- [c5]Sandeep K. Gupta, Dhiraj K. Pradhan: A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342
- 1987
- [j16]Israel Koren, Dhiraj K. Pradhan: Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems. IEEE Trans. Computers 36(3): 344-355 (1987)
- [c4]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan: Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. ISCA 1987: 224-231
- 1985
- [j15]Dhiraj K. Pradhan: Dynamically Restructurable Fault-Tolerant Processor Network Architectures. IEEE Trans. Computers 34(5): 434-447 (1985)
- [c3]Maheswara R. Samatham, Dhiraj K. Pradhan: The de Bruijn Multiprocessor Network: A Versatile Sorting Network. ISCA 1985: 360-367
- 1983
- [j14]Dhiraj K. Pradhan: Sequential Network Design Using Extra Inputs for Fault Detection. IEEE Trans. Computers 32(3): 319-323 (1983)
- 1982
- [j13]Bella Bose, Dhiraj K. Pradhan: Optimal Unidirectional Error Detecting/Correcting Codes. IEEE Trans. Computers 31(6): 564-568 (1982)
- [j12]Dhiraj K. Pradhan, Sudhakar M. Reddy: A Fault-Tolerant Communication Architecture for Distributed Systems. IEEE Trans. Computers 31(9): 863-870 (1982)
- [c2]Dhiraj K. Pradhan: On a Class of Fault-Tolerant Multiprocessor Network Architectures. ICDCS 1982: 302-311
- 1981
- [c1]
- 1980
- [j11]Kolar L. Kodandapani, Dhiraj K. Pradhan: Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets. IEEE Trans. Computers 29(1): 55-59 (1980)
- [j10]Dhiraj K. Pradhan: A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications. IEEE Trans. Computers 29(6): 471-481 (1980)
- [j9]Dhiraj K. Pradhan, Kolar L. Kodandapani: A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines. IEEE Trans. Computers 29(9): 777-791 (1980)
1970 – 1979
- 1978
- [j8]Dhiraj K. Pradhan: Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays. IEEE Trans. Computers 27(2): 181-187 (1978)
- [j7]Dhiraj K. Pradhan: A Theory of Galois Switching Functions. IEEE Trans. Computers 27(3): 239-248 (1978)
- [j6]Dhiraj K. Pradhan: Asynchronous State Assignments with Unateness Properties and Fault-Secure Design. IEEE Trans. Computers 27(5): 396-404 (1978)
- [j5]Dhiraj K. Pradhan: Fault-Tolerant Asynchronous Networks Using Read-Only Memories. IEEE Trans. Computers 27(7): 674-679 (1978)
- 1977
- [j4]L. C. Chang, Dhiraj K. Pradhan: A graph-structural approach for the generalization of data management systems. Inf. Sci. 12(1): 1-18 (1977)
- [j3]M. Y. Hsiao, Arvind M. Patel, Dhiraj K. Pradhan: Store Address Generator with On-Line Fault-Detection Capability. IEEE Trans. Computers 26(11): 1144-1151 (1977)
- 1976
- [j2]Dhiraj K. Pradhan, Sudhakar M. Reddy: Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. IEEE Trans. Computers 25(9): 945-949 (1976)
- 1975
- [j1]Dhiraj K. Pradhan, Arvind M. Patel: Reed-Muller Like Canonic Forms for Multivalued Functions. IEEE Trans. Computers 24(2): 206-210 (1975)
Coauthor Index
[c126] [j85] [c125] [c124] [c123] [j83] [j82] [j79] [j78] [c122] [c121] [c120] [j77] [j76] [j75] [j71] [c115] [c114] [c112] [c111] [j70] [j69] [c109] [c107] [c104] [j66] [j65] [j63] [c103] [c102] [c100] [c99] [c98] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c88] [c86] [c84] [c82] [c80] [c79] [c77] [c72] [c71] [c70] [c68] [c67]
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last updated on 2013-05-19 19:30 CEST by the dblp team