| 2013 | ||
|---|---|---|
| j29 | Gianluca Dini, Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda: A Social-Feedback Enriched Interface for Software Download. JOEUC 25(1): 24-42 (2013) | |
| 2012 | ||
| j28 | Massimiliano Annoni, Alessandro Bardine, Stefano Campanelli, Pierfrancesco Foglia, Cosimo Antonio Prete: A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error. Computer-Aided Design 44(6): 509-521 (2012) | |
| c28 | Stefano Campanelli, Pierfrancesco Foglia, Cosimo Antonio Prete: Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution. ETFA 2012: 1-8 | |
| 2011 | ||
| j27 | Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete: Eighth MEDEA Workshop. T. HiPEAC 3: 91-92 (2011) | |
| r2 | Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas: NUMA Caches. Encyclopedia of Parallel Computing 2011: 1329-1338 | |
| 2010 | ||
| j26 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete: Way adaptable D-NUCA caches. IJHPSA 2(3/4): 215-228 (2010) | |
| c27 | Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni: Re-NUCA: Boosting CMP Performance Through Block Replication. DSD 2010: 199-206 | |
| c26 | Alessandro Bardine, Stefano Campanelli, Pierfrancesco Foglia, Cosimo Antonio Prete: NURBS interpolator with confined chord error and tangential and centripetal acceleration control. ICUMT 2010: 489-496 | |
| c25 | Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete: Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. SBAC-PAD 2010: 87-94 | |
| 2009 | ||
| j25 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete: Impact of on-chip network parameters on nuca cache performances. IET Computers & Digital Techniques 3(5): 501-512 (2009) | |
| c24 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete: A power-efficient migration mechanism for D-NUCA caches. DATE 2009: 598-601 | |
| c23 | Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas: An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. DSD 2009: 26-33 | |
| c22 | Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas: Analysis of Performance Dependencies in NUCA-Based CMP Systems. SBAC-PAD 2009: 49-56 | |
| 2008 | ||
| c21 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström: Leveraging Data Promotion for Low Power D-NUCA Caches. DSD 2008: 307-316 | |
| c20 | Alessio Bechini, Cosimo Antonio Prete: Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message. SAC 2008: 1476 | |
| c19 | Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete: Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. SBAC-PAD 2008: 167-174 | |
| 2007 | ||
| j24 | Pierfrancesco Foglia, F. Giuntoli, Cosimo Antonio Prete, Michele Zanda: Assisting e-government users with animated talking faces. Interactions 14(1): 24-26 (2007) | |
| j23 | Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete: MEmory performance: DEaling with applications, systems and architecture. SIGARCH Computer Architecture News 35(4): 4-5 (2007) | |
| j22 | Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström: Improving power efficiency of D-NUCA caches. SIGARCH Computer Architecture News 35(4): 53-58 (2007) | |
| r1 | Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda: Modelling Public Administration Portals. Encyclopedia of Portal Technologies and Applications 2007: 606-614 | |
| 2006 | ||
| j21 | Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete: Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embedded Computing 2(1): 1-3 (2006) | |
| j20 | Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Memory performance: dealing with applications, systems and architecture. SIGARCH Computer Architecture News 34(1): 1-2 (2006) | |
| j19 | Alessandro Bardine, Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete: Analysis of embedded video coder systems: a system-level approach. SIGARCH Computer Architecture News 34(1): 71-76 (2006) | |
| c18 | Alessio Bechini, François Bodin, Cosimo Antonio Prete: Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2006: 889-890 | |
| 2005 | ||
| j18 | Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete: A cache design for high performance embedded systems. J. Embedded Computing 1(4): 587-597 (2005) | |
| j17 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distrib. Comput. 65(3): 289-306 (2005) | |
| j16 | Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete: Guests editor's introduction. SIGARCH Computer Architecture News 33(3): 1-2 (2005) | |
| j15 | Sandro Bartolini, Cosimo Antonio Prete: Optimizing instruction cache performance of embedded systems. ACM Trans. Embedded Comput. Syst. 4(4): 934-965 (2005) | |
| c17 | Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete: A NUCA Model for Embedded Systems Cache Design. ESTImedia 2005: 41-46 | |
| c16 | Alessio Bechini, François Bodin, Cosimo Antonio Prete: Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2005: 836-837 | |
| c15 | Cosimo Antonio Prete, Pierfrancesco Foglia, Michele Zanda: An Innovative Tool to Easily Get Usable Web Sites. WEBIST 2005: 373-376 | |
| 2004 | ||
| j14 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Speeding-up multiprocessors running DBMS workloads through coherence protocols. IJHPCN 1(1/2/3): 17-32 (2004) | |
| j13 | Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete: Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro 24(4): 8-9 (2004) | |
| j12 | Sandro Bartolini, Cosimo Antonio Prete: A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. SIGARCH Computer Architecture News 32(3): 70-77 (2004) | |
| c14 | Alessio Bechini, Cosimo Antonio Prete: Editorial message for the special track on embedded systems: applications, solutions, and techniques. SAC 2004: 819-820 | |
| 2003 | ||
| j11 | Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete: Fine-grain design space exploration for a cartographic SoC multiprocessor. SIGARCH Computer Architecture News 31(1): 85-92 (2003) | |
| c13 | ||
| 2002 | ||
| j10 | Sandro Bartolini, Cosimo Antonio Prete: A cache-aware program transformation technique suitable for embedded systems. Information & Software Technology 44(13): 783-795 (2002) | |
| j9 | Alessio Bechini, Cosimo Antonio Prete: Performance-steered design of software architectures for embedded multicore systems. Softw., Pract. Exper. 32(12): 1155-1173 (2002) | |
| c12 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops 2002: 134-146 | |
| c11 | Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete: Use of a CORBA/RMI gateway: characterization of communication overhead. Workshop on Software and Performance 2002: 150-156 | |
| 2001 | ||
| j8 | Alessio Bechini, Cosimo Antonio Prete: Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation. Future Generation Comp. Syst. 18(2): 307-316 (2001) | |
| j7 | Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, M. Valero: Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Computer Architecture News 29(5): 9-12 (2001) | |
| c10 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS 2001 | |
| c9 | Sandro Bartolini, Cosimo Antonio Prete: An Object Level Transformation Technique to Improve the Performance of Embedded Applications. SCAM 2001: 26-34 | |
| 2000 | ||
| c8 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS 2000 | |
| 1999 | ||
| j6 | Roberto Giorgi, Cosimo Antonio Prete: PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 10(7): 742-763 (1999) | |
| c7 | Alessio Bechini, Raffaele Lapadula, Cosimo Antonio Prete: Dealing with Non-Determinism in Communications within Java Applications. EUROMICRO 1999: 2350- | |
| c6 | Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete: Process Migration Effects on Memory Performance of Multiprocessor. HiPC 1999: 133-142 | |
| 1997 | ||
| c5 | Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi: A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) 1997: 266-275 | |
| 1996 | ||
| c4 | Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina: A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO 1996: 207-214 | |
| 1995 | ||
| j5 | Alberto Bartoli, Gianluca Dini, Marco Luise, G. Pazzaglia, Cosimo Antonio Prete, Aldo N. D'Andrea: Reusing sequential software in a distributed environment. Distributed Systems Engineering 2(1): 2-13 (1995) | |
| j4 | Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi: A Selective Invalidation Strategy for Cache Coherence. IEICE Transactions 78-D(10): 1316-1320 (1995) | |
| j3 | Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi: A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 6(9): 915-929 (1995) | |
| c3 | Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina: Reducing coherence-related overhead in multiprocessor systems. PDP 1995: 444-451 | |
| 1994 | ||
| c2 | Cosimo Antonio Prete: Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories. CSEE 1994: 317-327 | |
| 1992 | ||
| c1 | Cosimo Antonio Prete: A process cache memory for tightly coupled multiprocessor systems. ACM Southeast Regional Conference 1992: 131-138 | |
| 1990 | ||
| j2 | Paolo Ancilotti, Beatrice Lazzerini, Cosimo Antonio Prete, Maurizio Sacchi: A Distributed Commit Protocol for a Multicomputer System. IEEE Trans. Computers 39(5): 718-724 (1990) | |
| 1985 | ||
| j1 | Paolo Corsini, Cosimo Antonio Prete, Luca Simoncini: MuTEAM: An experience in the design of robust multiprocessor systems. Comput. Syst. Sci. Eng. 1(1): 23-35 (1985) | |
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